EVAL-ADRV9002

https://media.githubusercontent.com/media/analogdevicesinc/documentation/adrv9002/docs/solutions/reference-designs/adrv9002/images/ADRV9002-SP-TAG-chip-illustration.png

Overview

Important

The ADRV9001 is the family designator assigned to the System Development User Guide (UG-1828) for new ADRV9002, ADRV9003, ADRV9004, and upcoming additional family members. Thus, throughout this document, ADRV9001 designator may be used to refer to either ADRV9002, ADRV9003 or ADRV9004.

The ADRV9002 is a highly integrated RF transceiver that has dual-channel transmitters, dual-channel receivers, integrated synthesizers, and digital signal processing functions.

The ADRV9002 is a high performance, highly linear, high dynamic range transceiver designed for performance vs. power consumption system optimization. The device is configurable and ideally suited to demanding, low power, portable and battery powered equipment. The ADRV9002 operates from 30 MHz to 6000 MHz and covers the UHF, VHF, industrial, scientific, and medical (ISM) bands, and cellular frequency bands in narrow-band (kHz) and wideband operation up to 40 MHz. The ADRV9002 is capable of both TDD and FDD operation.

The transceiver consists of direct conversion signal paths with state-of-the-art noise figure and linearity. Each complete receiver and transmitter subsystem includes dc offset correction, quadrature error correction (QEC), and programmable digital filters, which eliminate the need for these functions in the digital baseband. In addition, several auxiliary functions, such as auxiliary analog-to-digital converters (ADCs), auxiliary digital-to-analog converters (DACs), and general-purpose inputs/outputs (GPIOs), are integrated to provide additional monitoring and control capability.

Features:

  • 2 × 2 highly integrated transceiver

  • Frequency range of 30 MHz to 6000 MHz

  • Transmitter and receiver bandwidth from 12 kHz to 40 MHz

  • Two fully integrated, fractional-N, RF synthesizers

  • LVDS and CMOS synchronous serial data interface options

  • Low power monitor and sleep modes

  • Multichip synchronization capabilities

  • Fast frequency hopping

  • Dynamic profile switching for dynamic data rates and sample rates

  • Fully integrated DPD for narrow-band and wideband waveforms

  • Fully programmable via a 4-wire SPI

  • 12 mm × 12 mm, 196-ball CSP_BGA

Applications:

  • Mission critical communications

  • Very high frequency (VHF), ultrahigh frequency (UHF), and cellular to 6 GHz

  • Time division duplexing (TDD) and frequency division duplexing (FDD) applications

EVAL-ADRV9002 looks like this, with 2x ADCs and 2x DACs. The evaluation boards are available in two variants: ADRV9002NP/W1/PCBZ (narrowband) and ADRV9002NP/W2/PCBZ (wideband).

https://media.githubusercontent.com/media/analogdevicesinc/documentation/adrv9002/docs/solutions/reference-designs/adrv9002/images/eval-adrv9002.gif

Recommendation

To better understand the ADRV9002, we recommend to use the EVAL-ADRV9002 evaluation board.

Table of contents

  1. Using the evaluation board/full stack reference design that we offer:

    1. User guide - what you need to know about the evaluation board

    2. Prerequisites - what you need to get started

    3. ADRV9001/2 Quick Start Guides:

      1. Using the ZedBoard

      2. Using the ZC706

      3. Using the ZCU102

      4. Using the Arria 10 SoC

    4. Configure an SD Card with Kuiper

    5. Software Solutions

      1. IIO Oscilloscope

      2. ADRV9002 Plugin Description

      3. Profile Generation using TES

      4. Scopy

      5. ADRV9002 Scopy Plugin

      6. Libiio command line utility

      7. Python Interfaces

      8. ADRV9002 Python Example

  2. Design with the ADRV9002

    1. Block diagram

      1. ADRV9002 product page

      2. EVAL-ADRV9002 product page

    2. Hardware in the Loop / How to design your own custom BaseBand

      1. GNU Radio

      2. Transceiver Toolbox

    3. Resources for designing a custom ADRV9002-based platform software

      1. For Linux software:

        1. About the device driver:

          1. AXI ADC HDL

          2. AXI DAC HDL

          3. AXI DMAC

          4. ADRV9002

          5. ADRV9002 Customization

        2. About the device tree:

          1. Customizing the device tree on the target

      2. For no-OS software:

        1. ADRV9001 no-OS Example Project

        2. ADRV9002 no-OS Driver

        3. no-OS IIO support

      3. FPGA Resources:

        1. HDL reference design which you must use in your FPGA.

        2. AXI ADRV9001

        3. HDL User Guide

      4. Testbench:

        1. ADRV9001 Testbench

        2. ADRV9001

Block diagram

https://media.githubusercontent.com/media/analogdevicesinc/documentation/adrv9002/docs/solutions/reference-designs/adrv9002/images/adrv9002-fbl.png

Videos

ADRV9002 RF Agile Transceiver Overview

Video

ADRV9002 Dual, Narrow and Wideband Integrated Transceiver

Video

ADI articles

MathWorks webinars

  1. Modelling and Simulating Analog Devices’ RF Transceivers with MATLAB and SimRF

  2. Getting Started with Software-Defined Radio using MATLAB and Simulink

Additional information

Four Quick Steps to Production - SDR Prototyping Platform Series:

  1. Part 1—The Analog Devices/Xilinx SDR Rapid Prototyping Platform: Its Capabilities, Benefits, and Tools

  2. Part 2—Mode S Detection and Decoding Using MATLAB and Simulink

  3. Part 3—Mode S Signals Decoding Algorithm Validation Using Hardware in the Loop

  4. Part 4—Rapid Prototyping Using the Zynq SDR Kit and Simulink Code Generation Workflow

SDR Signal Chains documentation - the math behind the RF:

Help and support

People who follow the flow that is outlined have a much better experience. However, like many things, documentation is never as complete as it should be. If you have any questions, feel free to ask on the EngineerZone technical support community, but before that, please make sure you read our documentation thoroughly.

Please use the appropriate support forum for your question:

  • For hardware technical support, please use the: EngineerZone

  • For Evaluation System Software support (TES GUI, ADRV9001 API driver, etc.), please use the: EngineerZone

  • For questions regarding the HDL reference design, please use the: EngineerZone

  • For questions regarding the ADI Linux distribution, the Linux drivers, or the device trees for the ADRV9001/2 based platforms, please use the: EngineerZone

  • For questions regarding the no-OS drivers for ADRV9001/2, please use the: EngineerZone

Warning

All the products described on this page include ESD (electrostatic discharge) sensitive devices. Electrostatic charges as high as 4000V readily accumulate on the human body or test equipment and can discharge without detection. Although the boards feature ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. This includes removing static charge on external equipment, cables, or antennas before connecting to the device.