AXI ADRV9001
The AXI ADRV9001 IP Core can be used to interface the ADRV9001 family, meaning:
This documentation only covers the IP core and requires that one must be familiar with the device for a complete and better understanding.
More about the generic framework interfacing ADCs that contains the up_adc_channel and up_adc_common modules can be read in Generic AXI ADC. Regarding the DAC, more information related to its generic framework can be found at Generic AXI DAC.
Features
AXI-based configuration
Supports both Altera and AMD Xilinx devices
LVDS and CMOS synchronous data interface options
PRBS monitoring
DC filtering
IQ correction
Programmable line delays (AMD)
Receive and transmit loop backs
Internal DDS
DAC selectable input source: DDS/DMA/ADC/TEST_RAMP
Files
Name |
Description |
---|---|
Verilog source for 4-port aligner. |
|
Verilog source for 8-port aligner. |
|
Verilog source packing two input beats into one. |
|
Verilog source for the RX Link. |
|
Verilog source for the RX Serdes Interface. |
|
Verilog source for the TX Link. |
|
Verilog source for the TX Serdes Interface. |
|
Verilog source for the AXI ADRV9001 core. |
|
Verilog source for the ADRV9001 interface module. |
|
Verilog source for the ADRV9001 RX channel. |
|
Verilog source for the AXI ADRV9001 RX Interface. |
|
Verilog source for the Transceiver TDD Control. |
|
Verilog source for the ADRV9001 TX channel. |
|
Verilog source for the AXI ADRV9001 TX Interface. |
|
Verilog source for the AXI ADRV9001. |
|
TCL script to generate the Vivado IP-integrator project. |
Block diagram
Functional Description
The axi_adrv9001 core’s architecture contains:
Wrapper top module
Interface module
Receive PHY (CMOS or LVDS interface)
Transmit PHY (CMOS or LVDS interface)
TPL (core), containing:
Receive - common receive module, containing:
ADC channel processing - RX channel modules, one for each channel
data processing modules ( DC Filter, IQ Correction and Data Format Control)
ADC PN Monitor for interface validation
Transmit module, containing:
DAC channel processing modules, one for each channel
Different data generators (DDS, ramp pattern)
ADC PN Generator for interface validation
AXI control and status modules.
Physical Interface
The following operation modes are supported by the physical layer (PHY). CMOS (CSSI) and LVDS (LSSI) selection is done through a synthesis parameter. Other parameters (column B, G, H) can be modified at run time, preferably while the core is in reset.
A |
B |
C |
D |
E |
F |
G |
H |
---|---|---|---|---|---|---|---|
CSSI 1-lane |
1 |
32 |
80 |
80 |
2.5 |
SDR |
8 |
CSSI 1-lane |
1 |
32 |
160 |
80 |
5 |
DDR |
4 |
CSSI 1-lane [1] |
1 |
16 |
80 |
80 |
— |
SDR |
4 |
CSSI 1-lane [1] |
1 |
16 |
160 |
80 |
— |
DDR |
2 |
CSSI 1-lane [2] |
1 |
8 |
80 |
80 |
— |
SDR |
2 |
CSSI 1-lane [2] |
1 |
8 |
160 |
80 |
— |
DDR |
1 |
CSSI 4-lane |
4 |
8 |
80 |
80 |
10 |
SDR |
2 |
CSSI 4-lane |
4 |
8 |
160 |
80 |
20 |
DDR |
1 |
LSSI 1-lane |
1 |
32 |
983.04 |
491.52 |
30.72 |
DDR |
4 |
LSSI 2-lane |
2 |
16 |
983.04 |
491.52 |
61.44 |
DDR |
2 |
Columns description:
A - SSI Modes
B - Data Lanes Per Channel
C - Serialization factor Per data lane
D - Max data lane rate (MHz)
E - Max Clock rate (MHz)
F - Max Sample Rate for I/Q (MHz)
G - Data Type
H - User Interface Clock to Sample Clock ratio (aka DDS Rate) for Xilinx devices
The following equations apply:
Where:
MaxDataLaneRate - number of bits transferred in a second per active lane
MaxClockRate - the source-synchronous interface clock frequency
UserInterfaceClock - the frequency of the clock the user interface logic is connected
InternalDivider - the division factor with which the source-synchronous interface clock is divided, to get the user interface clock. This is implementation-specific. Xilinx CMOS and LVDS = 4; Intel CMOS = 1
Since the UserInterfaceClock (column H) is an integer multiple of the MaxSampleRateForIQ, the interface towards the user logic has a valid qualifier which is not active on every clock cycle.
Requirements
Rx1 clock and Rx2 clock should be length matched
Clock and data in SSI interface must be length matched
Xilinx Physical interface
RX Component mode
For Rx interfaces, the source-synchronous associated clock is used to sample the input data. Software configuration is required, which is described in Configure ADC common interface section. Input delays of the FPGA or output delays of the ADRV9001 can be tuned by software for optimized sampling.
TX Using dedicated clock
For Tx interfaces, the clock received from the transceiver is used to drive the output data. Software configuration is required for clock rate selection, which is described in Configure DAC common interface section. Input delays of the ADRV9001 can be tuned by software for optimized sampling.
Configure DAC common interface
Register 0x0048 REG_CNTRL_2
[12:8] - NUM_LANES (new) - number of active lanes (1 : CSSI 1-lane, LSSI 1-lane, 2 : LSSI 2-lane, 4 : CSSI 4-lane)
[14] - SYMB_8_16B (new) - select number of bits for symbol format mode (1 represents 8b, 0 represents 16b)
[15] - SYMB_OP (new) - select symbol data format mode
[16] - SDR_DDR_N (new) - interface type (1 represents SDR, 0 represents DDR)
Register 0x04c REG_RATECNTRL
[7:0] RATE - must be set according to column H of the table
Configure ADC common interface
Register 0x0044 REG_CNTRL
[12:8] - NUM_LANES (new) - number of active lanes (1 : CSSI 1-lane, LSSI 1-lane, 2 : LSSI 2-lane, 4 : CSSI 4-lane)
[14] - SYMB_8_16B (new) - select number of bits for symbol format mode (1 represents 8b, 0 represents 16b)
[15] - SYMB_OP (new) - select symbol data format mode
[16] - SDR_DDR_N (new) - interface type ( 1 represents SDR, 0 represents DDR)
Configuration Parameters
Name |
Description |
Default Value |
Choices/Range |
---|---|---|---|
ID |
Core ID should be unique for each IP in the system |
0 |
|
CMOS_LVDS_N |
Defines the physical interface type, set 1 for CMOS and 0 for LVDS |
0 |
|
TDD_DISABLE |
By setting this parameter, the TDD control will not be implemented in the core |
0 |
|
DDS_DISABLE |
If resource utilization is a concern, by setting this parameter you can remove the dual tone DDS logic from the Tx channels. This will reduce resource utilization significantly, but will lose the ability to generate a test tone |
0 |
|
INDEPENDENT_1R1T_SUPPORT |
0 - Rx2 (adc_2_*) and Tx2 (dac_2_*) data channels will be disabled; RX2 TPL, TX2 TPL cores are disabled. 1 - Allows independent control of Rx2/Tx2 PHY either from Rx12/Tx12 TPL or Rx2/Tx2 TPL blocks; |
1 |
|
COMMON_2R2T_SUPPORT |
0 - puts the Rx12/Tx12 TPL in R1_MODE, having access only to Rx1/Tx1 PHYs; 1 - Allows Rx12/Tx12 TPL to operate in 2R 2T mode having control over Rx2/Tx2 PHY |
1 |
|
DISABLE_RX1_SSI |
Setting this parameter disables RX1 interface, PHY Link and TPL |
False |
|
DISABLE_TX1_SSI |
Setting this parameter disables TX1 interface, PHY Link and TPL |
0 |
|
DISABLE_RX2_SSI |
Setting this parameter disables RX2 interface, PHY Link and TPL |
False |
|
DISABLE_TX2_SSI |
Setting this parameter disables TX2 interface, PHY Link and TPL |
0 |
|
RX_USE_BUFG |
Used in case of Xilinx 7 series devices; If set, will insert a global clock buffer on the Rx clock path. Useful if user logic does not fit in a clock region |
0 |
|
TX_USE_BUFG |
Used in case of Xilinx 7 series devices; If set, will insert a global clock buffer on the Tx clock path. Useful if user logic does not fit in a clock region |
0 |
|
IODELAY_CTRL |
Iodelay Ctrl. |
1 |
|
IODELAY_ENABLE |
Iodelay Enable. |
1 |
|
IO_DELAY_GROUP |
The delay group name which is set for the delay controller |
dev_if_delay_group |
|
FPGA_TECHNOLOGY |
Auto populated by IPI |
0 |
Unknown (0), 7series (1), ultrascale (2), ultrascale+ (3), versal (4) |
FPGA_FAMILY |
Auto populated by IPI |
0 |
Unknown (0), artix (1), kintex (2), virtex (3), zynq (4), versalprime (5), versalaicore (6), versalpremium (7) |
SPEED_GRADE |
Auto populated by IPI |
0 |
Unknown (0), -1 (10), -1L (11), -1H (12), -1HV (13), -1LV (14), -2 (20), -2L (21), -2LV (22), -2MP (23), -2LVC (24), -2LVI (25), -3 (30) |
DEV_PACKAGE |
Auto populated by IPI |
0 |
Unknown (0), rf (1), fl (2), ff (3), fb (4), hc (5), fh (6), cs (7), cp (8), ft (9), fg (10), sb (11), rb (12), rs (13), cl (14), sf (15), ba (16), fa (17), fs (18), fi (19), vs (20), ls (21) |
EXT_SYNC |
DAC channel sync 1 = external or 0 = internal |
0 |
|
ENABLE_REF_CLK_MON |
Enable Ref Clk Mon. |
0 |
|
EN_RX_MCS_TO_STRB_M |
Enable 6’th MCS to Rx strobe measurment. |
0 |
|
USE_RX_CLK_FOR_TX1 |
Select the clock to drive the TX1 SSI interface 0 = TX1 dedicated clock 1 = RX1 SSI clock 2 = RX2 SSI clock |
0 |
Tx1 SSI ref clk (0), Rx1 SSI ref clk (1), Rx2 SSI ref clk (2) |
USE_RX_CLK_FOR_TX2 |
Select the clock to drive the TX2 SSI interface 0 = TX2 dedicated clock 1 = RX1 SSI clock 2 = RX2 SSI clock |
0 |
Tx2 SSI ref clk (0), Rx1 SSI ref clk (1), Rx2 SSI ref clk (2) |
Interface
Note
There are two ADC interfaces, composed of enable, valid, data and underflow signals. For simplicity, we will look only at the data part:
* - adc_1_data_i0/adc_1_data_i1
* - adc_2_data_i
Physical Port |
Logical Port |
Direction |
Dependency |
---|---|---|---|
s_axi_awaddr |
AWADDR |
in [15:0] |
|
s_axi_awprot |
AWPROT |
in [2:0] |
|
s_axi_awvalid |
AWVALID |
in |
|
s_axi_awready |
AWREADY |
out |
|
s_axi_wdata |
WDATA |
in [31:0] |
|
s_axi_wstrb |
WSTRB |
in [3:0] |
|
s_axi_wvalid |
WVALID |
in |
|
s_axi_wready |
WREADY |
out |
|
s_axi_bresp |
BRESP |
out [1:0] |
|
s_axi_bvalid |
BVALID |
out |
|
s_axi_bready |
BREADY |
in |
|
s_axi_araddr |
ARADDR |
in [15:0] |
|
s_axi_arprot |
ARPROT |
in [2:0] |
|
s_axi_arvalid |
ARVALID |
in |
|
s_axi_arready |
ARREADY |
out |
|
s_axi_rdata |
RDATA |
out [31:0] |
|
s_axi_rresp |
RRESP |
out [1:0] |
|
s_axi_rvalid |
RVALID |
out |
|
s_axi_rready |
RREADY |
in |
Physical Port |
Logical Port |
Direction |
Dependency |
---|---|---|---|
s_axi_aclk |
CLK |
in |
Physical Port |
Logical Port |
Direction |
Dependency |
---|---|---|---|
s_axi_aresetn |
RST |
in |
Physical Port |
Logical Port |
Direction |
Dependency |
---|---|---|---|
delay_clk |
CLK |
in |
Physical Port |
Logical Port |
Direction |
Dependency |
---|---|---|---|
adc_1_clk |
CLK |
out |
Physical Port |
Logical Port |
Direction |
Dependency |
---|---|---|---|
adc_2_clk |
CLK |
out |
INDEPENDENT_1R1T_SUPPORT == 1 && DISABLE_RX2_SSI == 0 |
Physical Port |
Logical Port |
Direction |
Dependency |
---|---|---|---|
dac_1_clk |
CLK |
out |
Physical Port |
Logical Port |
Direction |
Dependency |
---|---|---|---|
dac_2_clk |
CLK |
out |
INDEPENDENT_1R1T_SUPPORT == 1 && DISABLE_TX2_SSI == 0 |
Physical Port |
Logical Port |
Direction |
Dependency |
---|---|---|---|
adc_1_rst |
RST |
out |
Physical Port |
Logical Port |
Direction |
Dependency |
---|---|---|---|
adc_2_rst |
RST |
out |
INDEPENDENT_1R1T_SUPPORT == 1 && DISABLE_RX2_SSI == 0 |
Physical Port |
Logical Port |
Direction |
Dependency |
---|---|---|---|
dac_1_rst |
RST |
out |
Physical Port |
Logical Port |
Direction |
Dependency |
---|---|---|---|
dac_2_rst |
RST |
out |
INDEPENDENT_1R1T_SUPPORT == 1 && DISABLE_TX2_SSI == 0 |
Physical Port |
Direction |
Dependency |
Description |
---|---|---|---|
mssi_sync_in |
in |
||
ref_clk |
in |
||
mcs_in |
in |
||
mcs_out |
out |
||
mcs_src |
out |
||
tx_output_enable |
in |
||
rx1_dclk_in_n_NC |
in |
DISABLE_RX1_SSI == 0 |
rx1 CMOS - NC or LVDS - input clock N |
rx1_dclk_in_p_dclk_in |
in |
DISABLE_RX1_SSI == 0 |
rx1 CMOS or LVDS - input clock P |
rx1_idata_in_n_idata0 |
in |
DISABLE_RX1_SSI == 0 |
rx1 CMOS - I data 0 or LVDS - I data N |
rx1_idata_in_p_idata1 |
in |
DISABLE_RX1_SSI == 0 |
rx1 CMOS - I data 1 or LVDS - I data P |
rx1_qdata_in_n_qdata2 |
in |
DISABLE_RX1_SSI == 0 |
rx1 CMOS - Q data 2 or LVDS - Q data N |
rx1_qdata_in_p_qdata3 |
in |
DISABLE_RX1_SSI == 0 |
rx1 CMOS - Q data 3 or LVDS - Q data P |
rx1_strobe_in_n_NC |
in |
DISABLE_RX1_SSI == 0 |
rx1 CMOS - NC or LVDS - input strobe N |
rx1_strobe_in_p_strobe_in |
in |
DISABLE_RX1_SSI == 0 |
rx1 CMOS - strobe or LVDS - input strobe P |
rx2_dclk_in_n_NC |
in |
DISABLE_RX2_SSI == 0 |
rx2 CMOS - NC or LVDS - input clock N |
rx2_dclk_in_p_dclk_in |
in |
DISABLE_RX2_SSI == 0 |
rx2 CMOS or LVDS - input clock P |
rx2_idata_in_n_idata0 |
in |
DISABLE_RX2_SSI == 0 |
rx2 CMOS - I data 0 or LVDS - I data N |
rx2_idata_in_p_idata1 |
in |
DISABLE_RX2_SSI == 0 |
rx2 CMOS - I data 1 or LVDS - I data P |
rx2_qdata_in_n_qdata2 |
in |
DISABLE_RX2_SSI == 0 |
rx2 CMOS - Q data 2 or LVDS - Q data N |
rx2_qdata_in_p_qdata3 |
in |
DISABLE_RX2_SSI == 0 |
rx2 CMOS - Q data 3 or LVDS - Q data P |
rx2_strobe_in_n_NC |
in |
DISABLE_RX2_SSI == 0 |
rx2 CMOS - NC or LVDS - input strobe N |
rx2_strobe_in_p_strobe_in |
in |
DISABLE_RX2_SSI == 0 |
rx2 CMOS - strobe or LVDS - input strobe P |
tx1_dclk_out_n_NC |
out |
DISABLE_TX1_SSI == 0 |
tx1 CMOS - NC or LVDS - output clock N |
tx1_dclk_out_p_dclk_out |
out |
DISABLE_TX1_SSI == 0 |
tx1 CMOS or LVDS - output clock P |
tx1_dclk_in_n_NC |
in |
DISABLE_TX1_SSI == 0 |
tx1 CMOS - NC or LVDS - input clock N |
tx1_dclk_in_p_dclk_in |
in |
DISABLE_TX1_SSI == 0 |
tx1 CMOS or LVDS - input clock P |
tx1_idata_out_n_idata0 |
out |
DISABLE_TX1_SSI == 0 |
tx1 CMOS - I data 0 or LVDS - I data N |
tx1_idata_out_p_idata1 |
out |
DISABLE_TX1_SSI == 0 |
tx1 CMOS - I data 1 or LVDS - I data P |
tx1_qdata_out_n_qdata2 |
out |
DISABLE_TX1_SSI == 0 |
tx1 CMOS - Q data 2 or LVDS - Q data N |
tx1_qdata_out_p_qdata3 |
out |
DISABLE_TX1_SSI == 0 |
tx1 CMOS - Q data 3 or LVDS - Q data P |
tx1_strobe_out_n_NC |
out |
DISABLE_TX1_SSI == 0 |
tx1 CMOS - NC or LVDS - output strobe N |
tx1_strobe_out_p_strobe_out |
out |
DISABLE_TX1_SSI == 0 |
tx1 CMOS - strobe or LVDS - output strobe P |
tx2_dclk_out_n_NC |
out |
DISABLE_TX2_SSI == 0 |
tx2 CMOS - NC or LVDS - output clock N |
tx2_dclk_out_p_dclk_out |
out |
DISABLE_TX2_SSI == 0 |
tx2 CMOS or LVDS - output clock P |
tx2_dclk_in_n_NC |
in |
DISABLE_TX2_SSI == 0 |
tx2 CMOS - NC or LVDS - input clock N |
tx2_dclk_in_p_dclk_in |
in |
DISABLE_TX2_SSI == 0 |
tx2 CMOS or LVDS - input clock P |
tx2_idata_out_n_idata0 |
out |
DISABLE_TX2_SSI == 0 |
tx2 CMOS - I data 0 or LVDS - I data N |
tx2_idata_out_p_idata1 |
out |
DISABLE_TX2_SSI == 0 |
tx2 CMOS - I data 1 or LVDS - I data P |
tx2_qdata_out_n_qdata2 |
out |
DISABLE_TX2_SSI == 0 |
tx2 CMOS - Q data 2 or LVDS - Q data N |
tx2_qdata_out_p_qdata3 |
out |
DISABLE_TX2_SSI == 0 |
tx2 CMOS - Q data 3 or LVDS - Q data P |
tx2_strobe_out_n_NC |
out |
DISABLE_TX2_SSI == 0 |
tx2 CMOS - NC or LVDS - output strobe N |
tx2_strobe_out_p_strobe_out |
out |
DISABLE_TX2_SSI == 0 |
tx2 CMOS - strobe or LVDS - output strobe P |
rx1_enable |
out |
DISABLE_RX1_SSI == 0 |
out gpio rx1 enable pin |
rx2_enable |
out |
DISABLE_RX2_SSI == 0 |
out gpio rx2 enable pin |
tx1_enable |
out |
DISABLE_TX1_SSI == 0 |
out gpio tx1 enable pin |
tx2_enable |
out |
DISABLE_TX2_SSI == 0 |
out gpio tx2 enable pin |
adc_1_dovf |
in |
Data overflow, signal comming from pack |
|
adc_1_start_sync |
out |
||
adc_2_dovf |
in |
INDEPENDENT_1R1T_SUPPORT == 1 && DISABLE_RX2_SSI == 0 |
Data overflow, signal comming from pack |
adc_2_start_sync |
out |
INDEPENDENT_1R1T_SUPPORT == 1 && DISABLE_RX2_SSI == 0 |
|
dac_1_dunf |
in |
Data underflow, signal comming from upack |
|
dac_2_dunf |
in |
INDEPENDENT_1R1T_SUPPORT == 1 && DISABLE_TX2_SSI == 0 |
Data underflow, signal comming from upack |
tdd_sync |
in |
SYNC input for frame synchronization in TDD mode |
|
tdd_sync_cntr |
out |
SYNC output for frame synchronization in TDD mode |
|
gpio_rx1_enable_in |
in |
DISABLE_RX1_SSI == 0 |
input gpio rx1 enable |
gpio_rx2_enable_in |
in |
DISABLE_RX2_SSI == 0 |
input gpio rx2 enable |
gpio_tx1_enable_in |
in |
DISABLE_TX1_SSI == 0 |
input gpio tx1 enable |
gpio_tx2_enable_in |
in |
DISABLE_TX2_SSI == 0 |
input gpio tx2 enable |
adc_1_valid_i* |
out |
Indicates valid data at the channel 0 or 1, I component |
|
adc_1_enable_i* |
out |
If set, the channel 0 or 1, I component is enabled |
|
adc_1_data_i* |
out [15:0] |
Received data output for channel 0 or 1, I component |
|
adc_1_valid_q* |
out |
Indicates valid data at the channel 0 or 1, Q component |
|
adc_1_enable_q* |
out |
If set, the channel 0 or 1, Q component is enabled |
|
adc_1_data_q* |
out [15:0] |
Received data output for channel 0 or 1, Q component |
|
adc_2_valid_i* |
out |
INDEPENDENT_1R1T_SUPPORT == 1 && DISABLE_RX2_SSI == * |
Indicates valid data at the channel 1, I/Q component - used only if r1_mode is disabled |
adc_2_enable_i* |
out |
INDEPENDENT_1R1T_SUPPORT == 1 && DISABLE_RX2_SSI == * |
If set, the channel 1, I/Q component is enabled - used only if r1_mode is disabled |
adc_2_data_i* |
out [15:0] |
INDEPENDENT_1R1T_SUPPORT == 1 && DISABLE_RX2_SSI == * |
Received data output for channel 1, Q component - used only if r1_mode is disabled |
adc_2_valid_q* |
out |
INDEPENDENT_1R1T_SUPPORT == 1 && DISABLE_RX2_SSI == * |
Indicates valid data at the channel 1, I/Q component - used only if r1_mode is disabled |
adc_2_enable_q* |
out |
INDEPENDENT_1R1T_SUPPORT == 1 && DISABLE_RX2_SSI == * |
If set, the channel 1, I/Q component is enabled - used only if r1_mode is disabled |
adc_2_data_q* |
out [15:0] |
INDEPENDENT_1R1T_SUPPORT == 1 && DISABLE_RX2_SSI == * |
Received data output for channel 1, Q component - used only if r1_mode is disabled |
dac_1_valid_i* |
out |
Signals the DAC channel 0, I component, is ready to receive data |
|
dac_1_enable_i* |
out |
If set, the channel 0, I component is enabled |
|
dac_1_data_i* |
in [15:0] |
Data input for channel 0, I component |
|
dac_1_valid_q* |
out |
Signals the DAC channel 0, Q component, is ready to receive data |
|
dac_1_enable_q* |
out |
If set, the channel 0, Q component is enabled |
|
dac_1_data_q* |
in [15:0] |
Data input for channel 0, Q component |
|
dac_2_valid_i* |
out |
INDEPENDENT_1R1T_SUPPORT == 1 && DISABLE_TX2_SSI == * |
Signals the DAC channel 1, I/Q component - is ready to receive data - used only if r1_mode is disabled |
dac_2_enable_i* |
out |
INDEPENDENT_1R1T_SUPPORT == 1 && DISABLE_TX2_SSI == * |
If set, the channel 1, I/Q component is enabled - used only if r1_mode is disabled |
dac_2_data_i* |
in [15:0] |
INDEPENDENT_1R1T_SUPPORT == 1 && DISABLE_TX2_SSI == * |
Data input for channel 1, I/Q component - used only if r1_mode is disabled |
dac_2_valid_q* |
out |
INDEPENDENT_1R1T_SUPPORT == 1 && DISABLE_TX2_SSI == * |
Signals the DAC channel 1, I/Q component - is ready to receive data - used only if r1_mode is disabled |
dac_2_enable_q* |
out |
INDEPENDENT_1R1T_SUPPORT == 1 && DISABLE_TX2_SSI == * |
If set, the channel 1, I/Q component is enabled - used only if r1_mode is disabled |
dac_2_data_q* |
in [15:0] |
INDEPENDENT_1R1T_SUPPORT == 1 && DISABLE_TX2_SSI == * |
Data input for channel 1, I/Q component - used only if r1_mode is disabled |
Register Map
The register map of the core contains instances of several generic register maps like ADC common, ADC channel, DAC common, DAC channel etc. The following table presents the base addresses of each instance, after that can be found the detailed description of each generic register map. The absolute address of a register should be calculated by adding the instance base address to the registers relative address.
Register Map base addresses for axi_adrv9001
DWORD |
BYTE |
Name |
Description |
0x0000 |
0x0000 |
RX1 COMMON |
See the ADC Common table for more details |
0x0000 |
0x0000 |
RX1 CHANNELS |
See the ADC Channel table for more details |
0x0200 |
0x0800 |
RX1 DELAY CONTROL |
See the IO Delay Control table for more details |
0x0400 |
0x1000 |
RX2 COMMON |
See the ADC Common table for more details |
0x0400 |
0x1000 |
RX2 CHANNELS |
See the ADC Channel table for more details |
0x0600 |
0x1800 |
RX2 DELAY CONTROL |
See the IO Delay Control table for more details |
0x0800 |
0x2000 |
TX1 COMMON |
See the DAC Common table for more details |
0x0800 |
0x2000 |
TX1 CHANNELS |
See the DAC Channel table for more details |
0x1000 |
0x4000 |
TX2 COMMON |
See the DAC Common table for more details |
0x1000 |
0x4000 |
TX2 CHANNELS |
See the DAC Channel table for more details |
0x1200 |
0x4800 |
TDD1 CONTROL |
See the Transceiver TDD1 Control table for more details |
0x1300 |
0x4C00 |
TDD2 CONTROL |
See the Transceiver TDD2 Control table for more details |
DWORD |
BYTE |
Reg Name |
Description |
|||
---|---|---|---|---|---|---|
BITS |
Field Name |
Type |
Default Value |
Description |
||
0x0 |
0x0 |
VERSION |
Version and Scratch Registers |
|||
[31:0] |
VERSION |
RO |
0x00000000 |
Version number. Unique to all cores. |
||
0x1 |
0x4 |
ID |
Version and Scratch Registers |
|||
[31:0] |
ID |
RO |
0x00000000 |
Instance identifier number. |
||
0x2 |
0x8 |
SCRATCH |
Version and Scratch Registers |
|||
[31:0] |
SCRATCH |
RW |
0x00000000 |
Scratch register. |
||
0x3 |
0xc |
CONFIG |
Version and Scratch Registers |
|||
[0] |
IQCORRECTION_DISABLE |
RO |
0x0 |
If set, indicates that the IQ Correction module was not implemented. (as a result of a configuration of the IP instance) |
||
[1] |
DCFILTER_DISABLE |
RO |
0x0 |
If set, indicates that the DC Filter module was not implemented. (as a result of a configuration of the IP instance) |
||
[2] |
DATAFORMAT_DISABLE |
RO |
0x0 |
If set, indicates that the Data Format module was not implemented. (as a result of a configuration of the IP instance) |
||
[3] |
USERPORTS_DISABLE |
RO |
0x0 |
If set, indicates that the logic related to the User Data Format (e.g. decimation) was not implemented. (as a result of a configuration of the IP instance) |
||
[5] |
DELAY_CONTROL_DISABLE |
RO |
0x0 |
If set, indicates that the delay control is disabled for this IP. (as a result of a configuration of the IP instance) |
||
[6] |
DDS_DISABLE |
RO |
0x0 |
If set, indicates that the DDS is disabled for this IP. (as a result of a configuration of the IP instance) |
||
[7] |
CMOS_OR_LVDS_N |
RO |
0x0 |
CMOS or LVDS mode is used for the interface. (as a result of a configuration of the IP instance) |
||
[8] |
PPS_RECEIVER_ENABLE |
RO |
0x0 |
If set, indicates the PPS receiver is enabled. (as a result of a configuration of the IP instance) |
||
[10] |
USE_RX_CLK_FOR_TX |
RO |
0x1 |
|
||
[12] |
EXT_SYNC |
RO |
0x0 |
If set the transport layer cores (ADC/DAC) have implemented the support for external synchronization signal. |
||
[14] |
SELECTABLE_CLK |
RO |
0x1 |
If set indicates that axi_adrv9001 Rx to Tx selectable clock option is available. |
||
0x7 |
0x1c |
FPGA_INFO |
FPGA device information library/scripts/adi_intel_device_info_enc.tcl (Intel encoded values) library/scripts/adi_xilinx_device_info_enc.tcl (Xilinx encoded values) |
|||
[31:24] |
FPGA_TECHNOLOGY |
RO |
0x00 |
Encoded value describing the technology/generation of the FPGA device (arria 10/7series) |
||
[23:16] |
FPGA_FAMILY |
RO |
0x00 |
Encoded value describing the family variant of the FPGA device(e.g., SX, GX, GT or zynq, kintex, virtex) |
||
[15:8] |
SPEED_GRADE |
RO |
0x00 |
Encoded value describing the FPGA’s speed-grade |
||
[7:0] |
DEV_PACKAGE |
RO |
0x00 |
Encoded value describing the device package. The package might affect high-speed interfaces |
||
0x10 |
0x40 |
RSTN |
ADC Interface Control & Status |
|||
[0] |
RSTN |
RW |
0x0 |
Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core. |
||
0x11 |
0x44 |
CNTRL |
ADC Interface Control & Status |
|||
[16] |
SDR_DDR_N |
RW |
0x0 |
Interface type (1 represents SDR, 0 represents DDR) |
||
[15] |
SYMB_OP |
RW |
0x0 |
Select symbol data format mode (0x1) |
||
[14] |
SYMB_8_16B |
RW |
0x0 |
Select number of bits for symbol format mode (1 represents 8b, 0 represents 16b) |
||
[12:8] |
NUM_LANES |
RW |
0x00 |
Number of active lanes (1 : CSSI 1-lane, LSSI 1-lane, 2 : LSSI 2-lane, 4 : CSSI 4-lane). For AD7768, AD7768-4 and AD777x number of active lanes : 1/2/4/8 where supported. |
||
[3] |
SYNC |
RW |
0x0 |
Initialize synchronization between multiple ADCs |
||
[2] |
R1_MODE |
RW |
0x0 |
Select number of RF channels 1 (0x1) or 2 (0x0). |
||
[1] |
DDR_EDGESEL |
RW |
0x0 |
Select rising edge (0x0) or falling edge (0x1) for the first part of a sample (if applicable) followed by the successive edges for the remaining parts. This only controls how the sample is delineated from the incoming data post DDR registers. |
||
[0] |
PIN_MODE |
RW |
0x0 |
Select interface pin mode to be clock multiplexed (0x1) or pin multiplexed (0x0). In clock multiplexed mode, samples are received on alternative clock edges. In pin multiplexed mode, samples are interleaved or grouped on the pins at the same clock edge. |
||
0x12 |
0x48 |
CNTRL_2 |
ADC Interface Control & Status |
|||
[1] |
EXT_SYNC_ARM |
RW |
0x0 |
Setting this bit will arm the trigger mechanism sensitive to an external sync signal. Once the external sync signal goes high it synchronizes channels within a ADC, and across multiple instances. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears. |
||
[2] |
EXT_SYNC_DISARM |
RW |
0x0 |
Setting this bit will disarm the trigger mechanism sensitive to an external sync signal. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears. |
||
[8] |
MANUAL_SYNC_REQUEST |
RW |
0x0 |
Setting this bit will issue an external sync event if it is hooked up inside the fabric. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears. |
||
0x15 |
0x54 |
CLK_FREQ |
ADC Interface Control & Status |
|||
[31:0] |
CLK_FREQ |
RO |
0x00000000 |
Interface clock frequency. This is relative to the processor clock and in many cases is 100MHz. The number is represented as unsigned 16.16 format. Assuming a 100MHz processor clock the minimum is 1.523kHz and maximum is 6.554THz. The actual interface clock is CLK_FREQ * CLK_RATIO (see below). Note that the actual sampling clock may not be the same as the interface clock- software must consider device specific implementation parameters to calculate the final sampling clock. |
||
0x16 |
0x58 |
CLK_RATIO |
ADC Interface Control & Status |
|||
[31:0] |
CLK_RATIO |
RO |
0x00000000 |
Interface clock ratio - as a factor actual received clock. This is implementation specific and depends on any serial to parallel conversion and interface type (ddr/sdr/qdr). |
||
0x17 |
0x5c |
STATUS |
ADC Interface Control & Status |
|||
[3] |
PN_ERR |
RO |
0x0 |
If set, indicates pn error in one or more channels. |
||
[2] |
PN_OOS |
RO |
0x0 |
If set, indicates pn oos in one or more channels. |
||
[0] |
STATUS |
RO |
0x0 |
Interface status, if set indicates no errors. If not set, there are errors, software may try resetting the cores. |
||
0x22 |
0x88 |
UI_STATUS |
User Interface Status |
|||
[2] |
UI_OVF |
RW1C |
0x0 |
User Interface overflow. If set, indicates an overflow occurred during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit. |
||
0x28 |
0xa0 |
USR_CNTRL_1 |
ADC Interface Control & Status |
|||
[7:0] |
USR_CHANMAX |
RW |
0x00 |
This indicates the maximum number of inputs for the channel data multiplexers. User may add different processing modules post data capture as another input to this common multiplexer. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1). |
DWORD |
BYTE |
Reg Name |
Description |
|||
---|---|---|---|---|---|---|
BITS |
Field Name |
Type |
Default Value |
Description |
||
0x100 + 0x16*n |
0x400 + 0x58*n |
CHAN_CNTRLn |
ADC Interface Control & Status Where n is from 0 to 15. |
|||
[11] |
ADC_LB_OWR |
RW |
0x0 |
If set, forces ADC_DATA_SEL to 1, enabling data loopback |
||
[10] |
ADC_PN_SEL_OWR |
RW |
0x0 |
If set, forces ADC_PN_SEL to 0x9, device specific pn (e.g. ad9361) If both ADC_PN_TYPE_OWR and ADC_PN_SEL_OWR are set, they are ignored |
||
[9] |
IQCOR_ENB |
RW |
0x0 |
if set, enables IQ correction or scale correction. NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1). |
||
[8] |
DCFILT_ENB |
RW |
0x0 |
if set, enables DC filter (to disable DC offset, set offset value to 0x0). NOT-APPLICABLE if DCFILTER_DISABLE is set (0x1). |
||
[6] |
FORMAT_SIGNEXT |
RW |
0x0 |
if set, enables sign extension (applicable only in 2’s complement mode). The data is always sign extended to the nearest byte boundary. NOT-APPLICABLE if DATAFORMAT_DISABLE is set (0x1). |
||
[5] |
FORMAT_TYPE |
RW |
0x0 |
Select offset binary (0x1) or 2’s complement (0x0) data type. This sets the incoming data type and is required by the post processing modules for any data conversion. NOT-APPLICABLE if DATAFORMAT_DISABLE is set (0x1). |
||
[4] |
FORMAT_ENABLE |
RW |
0x0 |
Enable data format conversion (see register bits above). NOT-APPLICABLE if DATAFORMAT_DISABLE is set (0x1). |
||
[3] |
RESERVED |
RO |
0x0 |
Reserved for backward compatibility. |
||
[3] |
RESERVED |
RO |
0x0 |
Reserved for backward compatibility. |
||
[1] |
ADC_PN_TYPE_OWR |
RW |
0x0 |
If set, forces ADC_PN_SEL to 0x1, modified pn23 If both ADC_PN_TYPE_OWR and ADC_PN_SEL_OWR are set, they are ignored |
||
[0] |
ENABLE |
RW |
0x0 |
If set, enables channel. A 0x0 to 0x1 transition transfers all the control signals to the respective channel processing module. If a channel is part of a complex signal (I/Q), even channel is the master and the odd channel is the slave. Though a single control is used, both must be individually selected. |
||
0x101 + 0x16*n |
0x404 + 0x58*n |
CHAN_STATUSn |
ADC Interface Control & Status Where n is from 0 to 15. |
|||
[12] |
CRC_ERR |
RW1C |
0x0 |
CRC errors. If set, indicates CRC error. Software must first clear this bit before initiating a transfer and monitor afterwards. |
||
[11:4] |
STATUS_HEADER |
RO |
0x00 |
The status header sent by the ADC.(compatible with AD7768/AD7768-4/AD777x). |
||
[2] |
PN_ERR |
RW1C |
0x0 |
PN errors. If set, indicates spurious mismatches in sync state. This bit is cleared if OOS is set and is only indicates errors when OOS is cleared. |
||
[1] |
PN_OOS |
RW1C |
0x0 |
PN Out Of Sync. If set, indicates an OOS status. OOS is set, if 64 consecutive patterns mismatch from the expected pattern. It is cleared, when 16 consecutive patterns match the expected pattern. |
||
[0] |
OVER_RANGE |
RW1C |
0x0 |
If set, indicates over range. Note that over range is independent of the data path, it indicates an over range over a data transfer period. Software must first clear this bit before initiating a transfer and monitor afterwards. |
||
0x102 + 0x16*n |
0x408 + 0x58*n |
CHAN_RAW_DATAn |
ADC Raw Data Reading Where n is from 0 to 15. |
|||
[31:0] |
ADC_READ_DATA |
RO |
0x00000000 |
Raw data read from the ADC. |
||
0x104 + 0x16*n |
0x410 + 0x58*n |
CHAN_CNTRLn_1 |
ADC Interface Control & Status Where n is from 0 to 15. |
|||
[31:16] |
DCFILT_OFFSET |
RW |
0x0000 |
DC removal (if equipped) offset. This is a 2’s complement number added to the incoming data to remove a known DC offset. NOT-APPLICABLE if DCFILTER_DISABLE is set (0x1). |
||
[15:0] |
DCFILT_COEFF |
RW |
0x0000 |
DC removal filter (if equipped) coefficient. The format is 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if DCFILTER_DISABLE is set (0x1). |
||
0x105 + 0x16*n |
0x414 + 0x58*n |
CHAN_CNTRLn_2 |
ADC Interface Control & Status Where n is from 0 to 15. |
|||
[31:16] |
IQCOR_COEFF_1 |
RW |
0x0000 |
IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the scale value and the format is 1.1.14 (sign, integer and fractional bits). If matrix multiplication is used, this is the channel I coefficient and the format is 1.1.14 (sign, integer and fractional bits). If SCALECORRECTION_ONLY is set, this implements the scale value correction for the current channel with the format 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1). |
||
[15:0] |
IQCOR_COEFF_2 |
RW |
0x0000 |
IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the offset value and the format is 2’s complement. If matrix multiplication is used, this is the channel Q coefficient and the format is 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1). |
||
0x106 + 0x16*n |
0x418 + 0x58*n |
CHAN_CNTRLn_3 |
ADC Interface Control & Status Where n is from 0 to 15. |
|||
[19:16] |
ADC_PN_SEL |
RW |
0x0 |
Selects the PN monitor sequence type (available only if ADC supports it).
|
||
[3:0] |
ADC_DATA_SEL |
RW |
0x0 |
Selects the data source to DMA. 0x0: input data (ADC) 0x1: loopback data (DAC) |
||
0x108 + 0x16*n |
0x420 + 0x58*n |
CHAN_USR_CNTRLn_1 |
ADC Interface Control & Status Where n is from 0 to 15. |
|||
[25] |
USR_DATATYPE_BE |
RO |
0x0 |
The user data type format- if set, indicates big endian (default is little endian). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1). |
||
[24] |
USR_DATATYPE_SIGNED |
RO |
0x0 |
The user data type format- if set, indicates signed (2’s complement) data (default is unsigned). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1). |
||
[23:16] |
USR_DATATYPE_SHIFT |
RO |
0x00 |
The user data type format- the amount of right shift for actual samples within the total number of bits. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1). |
||
[15:8] |
USR_DATATYPE_TOTAL_BITS |
RO |
0x00 |
The user data type format- number of total bits used for a sample. The total number of bits must be an integer multiple of 8 (byte aligned). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1). |
||
[7:0] |
USR_DATATYPE_BITS |
RO |
0x00 |
The user data type format- number of bits in a sample. This indicates the actual sample data bits. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1). |
||
0x109 + 0x16*n |
0x424 + 0x58*n |
CHAN_USR_CNTRLn_2 |
ADC Interface Control & Status Where n is from 0 to 15. |
|||
[31:16] |
USR_DECIMATION_M |
RW |
0x0000 |
This holds the user decimation M value of the channel that is currently being selected on the multiplexer above. The total decimation factor is of the form M/N. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1). |
||
[15:0] |
USR_DECIMATION_N |
RW |
0x0000 |
This holds the user decimation N value of the channel that is currently being selected on the multiplexer above. The total decimation factor is of the form M/N. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1). |
DWORD |
BYTE |
Reg Name |
Description |
|||
---|---|---|---|---|---|---|
BITS |
Field Name |
Type |
Default Value |
Description |
||
0x0 + 0x1*n |
0x0 + 0x4*n |
DELAY_CONTROL_n |
Delay Control & Status Where n is from 0 to 15. |
|||
[4:0] |
DELAY_CONTROL_IO_n |
RW |
0x00 |
Tap value for input/output delay primitive of the n’th interface line. If the delay controller is not locked (indicate issues with delay_clk), the read-back value of this register will be 0xFFFFFFFF. Otherwise will be the last set up value. |
DWORD |
BYTE |
Reg Name |
Description |
|||
---|---|---|---|---|---|---|
BITS |
Field Name |
Type |
Default Value |
Description |
||
0x0 |
0x0 |
VERSION |
Version and Scratch Registers |
|||
[31:0] |
VERSION |
RO |
0x00000000 |
Version number. Unique to all cores. |
||
0x1 |
0x4 |
ID |
Version and Scratch Registers |
|||
[31:0] |
ID |
RO |
0x00000000 |
Instance identifier number. |
||
0x2 |
0x8 |
SCRATCH |
Version and Scratch Registers |
|||
[31:0] |
SCRATCH |
RW |
0x00000000 |
Scratch register. |
||
0x3 |
0xc |
CONFIG |
Version and Scratch Registers |
|||
[0] |
IQCORRECTION_DISABLE |
RO |
0x0 |
If set, indicates that the IQ Correction module was not implemented. (as a result of a configuration of the IP instance) |
||
[1] |
DCFILTER_DISABLE |
RO |
0x0 |
If set, indicates that the DC Filter module was not implemented. (as a result of a configuration of the IP instance) |
||
[2] |
DATAFORMAT_DISABLE |
RO |
0x0 |
If set, indicates that the Data Format module was not implemented. (as a result of a configuration of the IP instance) |
||
[3] |
USERPORTS_DISABLE |
RO |
0x0 |
If set, indicates that the logic related to the User Data Format (e.g. decimation) was not implemented. (as a result of a configuration of the IP instance) |
||
[5] |
DELAY_CONTROL_DISABLE |
RO |
0x0 |
If set, indicates that the delay control is disabled for this IP. (as a result of a configuration of the IP instance) |
||
[6] |
DDS_DISABLE |
RO |
0x0 |
If set, indicates that the DDS is disabled for this IP. (as a result of a configuration of the IP instance) |
||
[7] |
CMOS_OR_LVDS_N |
RO |
0x0 |
CMOS or LVDS mode is used for the interface. (as a result of a configuration of the IP instance) |
||
[8] |
PPS_RECEIVER_ENABLE |
RO |
0x0 |
If set, indicates the PPS receiver is enabled. (as a result of a configuration of the IP instance) |
||
[10] |
USE_RX1_CLK_FOR_TX |
RO |
0x1 |
If set indicates that the RX1 channel SSI clock is used for TXn ch SSI clock. |
||
[11] |
USE_RX2_CLK_FOR_TX |
RO |
0x1 |
If set indicates that the RX2 channel SSI clock is used for TXn ch SSI clock. |
||
[12] |
EXT_SYNC |
RO |
0x0 |
If set the transport layer cores (ADC/DAC) have implemented the support for external synchronization signal. |
||
[14] |
SELECTABLE_CLK |
RO |
0x1 |
If set indicates that axi_adrv9001 Rx to Tx selectable clock option is available. |
||
0x7 |
0x1c |
FPGA_INFO |
FPGA device information library/scripts/adi_intel_device_info_enc.tcl (Intel encoded values) library/scripts/adi_xilinx_device_info_enc.tcl (Xilinx encoded values) |
|||
[31:24] |
FPGA_TECHNOLOGY |
RO |
0x00 |
Encoded value describing the technology/generation of the FPGA device (arria 10/7series) |
||
[23:16] |
FPGA_FAMILY |
RO |
0x00 |
Encoded value describing the family variant of the FPGA device(e.g., SX, GX, GT or zynq, kintex, virtex) |
||
[15:8] |
SPEED_GRADE |
RO |
0x00 |
Encoded value describing the FPGA’s speed-grade |
||
[7:0] |
DEV_PACKAGE |
RO |
0x00 |
Encoded value describing the device package. The package might affect high-speed interfaces |
||
0x10 |
0x40 |
RSTN |
DAC Interface Control & Status |
|||
[0] |
RSTN |
RW |
0x0 |
Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core. |
||
0x11 |
0x44 |
CNTRL_1 |
DAC Interface Control & Status |
|||
[0] |
SYNC |
RW |
0x0 |
Setting this bit synchronizes channels within a DAC, and across multiple instances. This bit self clears. |
||
[1] |
EXT_SYNC_ARM |
RW |
0x0 |
Setting this bit will arm the trigger mechanism sensitive to an external sync signal. Once the external sync signal goes high it synchronizes channels within a DAC, and across multiple instances. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears. |
||
[2] |
EXT_SYNC_DISARM |
RW |
0x0 |
Setting this bit will disarm the trigger mechanism sensitive to an external sync signal. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears. |
||
[8] |
MANUAL_SYNC_REQUEST |
RW |
0x0 |
Setting this bit will issue an external sync event if it is hooked up inside the fabric. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears. |
||
0x12 |
0x48 |
CNTRL_2 |
DAC Interface Control & Status |
|||
[16] |
SDR_DDR_N |
RW |
0x0 |
Interface type (1 represents SDR, 0 represents DDR) |
||
[15] |
SYMB_OP |
RW |
0x0 |
Select data symbol format mode (0x1) |
||
[14] |
SYMB_8_16B |
RW |
0x0 |
Select number of bits for symbol format mode (1 represents 8b, 0 represents 16b) |
||
[12:8] |
NUM_LANES |
RW |
0x00 |
Number of active lanes (1 : CSSI 1-lane, LSSI 1-lane, 2 : LSSI 2-lane, 4 : CSSI 4-lane) |
||
[5] |
R1_MODE |
RW |
0x0 |
Select number of RF channels 1 (0x1) or 2 (0x0). |
||
[4] |
DATA_FORMAT |
RW |
0x0 |
Select data format 2’s complement (0x0) or offset binary (0x1). NOT-APPLICABLE if DAC_DP_DISABLE is set (0x1). |
||
[3:0] |
RESERVED |
NA |
0x0 |
Reserved |
||
0x13 |
0x4c |
RATECNTRL |
DAC Interface Control & Status |
|||
[7:0] |
RATE |
RW |
0x00 |
The effective dac rate (the maximum possible rate is dependent on the interface clock). The samples are generated at 1/RATE of the interface clock. |
||
0x15 |
0x54 |
STATUS1 |
DAC Interface Control & Status |
|||
[31:0] |
CLK_FREQ |
RO |
0x00000000 |
Interface clock frequency. This is relative to the processor clock and in many cases is 100MHz. The number is represented as unsigned 16.16 format. Assuming a 100MHz processor clock the minimum is 1.523kHz and maximum is 6.554THz. The actual interface clock is CLK_FREQ * CLK_RATIO (see below). Note that the actual sampling clock may not be the same as the interface clock- software must consider device specific implementation parameters to calculate the final sampling clock. |
||
0x16 |
0x58 |
STATUS2 |
DAC Interface Control & Status |
|||
[31:0] |
CLK_RATIO |
RO |
0x00000000 |
Interface clock ratio - as a factor actual received clock. This is implementation specific and depends on any serial to parallel conversion and interface type (ddr/sdr/qdr). |
||
0x18 |
0x60 |
DAC_CLKSEL |
DAC Interface Control & Status |
|||
[0] |
DAC_CLKSEL |
RW |
0x0 |
Allows changing of the clock polarity. Note: its default value is CLK_EDGE_SEL |
||
0x1a |
0x68 |
SYNC_STATUS |
DAC Synchronization Status register |
|||
[0] |
DAC_SYNC_STATUS |
RO |
0x0 |
DAC synchronization status. Will be set to 1 while waiting for the external synchronization signal This bit has an effect only the EXT_SYNC synthesis parameter is set. |
||
0x22 |
0x88 |
UI_STATUS |
User Interface Status |
|||
[1] |
UI_OVF |
RW1C |
0x0 |
User Interface overflow. If set, indicates an overflow occurred during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit. |
||
0x28 |
0xa0 |
USR_CNTRL_1 |
DAC User Control & Status |
|||
[7:0] |
USR_CHANMAX |
RW |
0x00 |
This indicates the maximum number of inputs for the channel data multiplexers. User may add different processing modules as inputs to the dac. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1). |
DWORD |
BYTE |
Reg Name |
Description |
|||
---|---|---|---|---|---|---|
BITS |
Field Name |
Type |
Default Value |
Description |
||
0x100 + 0x16*n |
0x400 + 0x58*n |
CHAN_CNTRLn_1 |
DAC Channel Control & Status (channel - 0) Where n is from 0 to 15. |
|||
[21:16] |
DDS_PHASE_DW |
RO |
0x00 |
The DDS phase data width offers the HDL parameter configuration with the same name. This information is used in conjunction with CHAN_CNTRL_9 and CHAN_CNTRL_10. More info at AD Direct Digital Synthesis. |
||
[15:0] |
DDS_SCALE_1 |
RW |
0x0000 |
The DDS scale for tone 1. Sets the amplitude of the tone. The format is 1.1.14 fixed point (signed, integer, fractional). The DDS in general runs on 16-bits, note that if you do use both channels and set both scale to 0x4000, it is over-range. The final output is (tone_1_fullscale * scale_1) + (tone_2_fullscale * scale_2). NOT-APPLICABLE if DDS_DISABLE is set (0x1). |
||
0x101 + 0x16*n |
0x404 + 0x58*n |
CHAN_CNTRLn_2 |
DAC Channel Control & Status (channel - 0) Where n is from 0 to 15. |
|||
[31:16] |
DDS_INIT_1 |
RW |
0x0000 |
The DDS phase initialization for tone 1. Sets the initial phase offset of the tone. NOT-APPLICABLE if DDS_DISABLE is set (0x1). |
||
[15:0] |
DDS_INCR_1 |
RW |
0x0000 |
Sets the frequency of the phase accumulator. Its value can be calculated by \(INCR = (f_{out} * 2^{16}) * clkratio / f_{if}\); where f_out is the generated output frequency, and f_if is the frequency of the digital interface, and clock_ratio is the ratio between the sampling clock and the interface clock. If DDS_PHASE_DW is greater than 16(from CHAN_CNTRL_1), the phase increment for tone 1 is extended in CHAN_CNTRL_9. NOT-APPLICABLE if DDS_DISABLE is set (0x1). |
||
0x102 + 0x16*n |
0x408 + 0x58*n |
CHAN_CNTRLn_3 |
DAC Channel Control & Status (channel - 0) Where n is from 0 to 15. |
|||
[15:0] |
DDS_SCALE_2 |
RW |
0x0000 |
The DDS scale for tone 2. Sets the amplitude of the tone. The format is 1.1.14 fixed point (signed, integer, fractional). The DDS in general runs on 16-bits, note that if you do use both channels and set both scale to 0x4000, it is over-range. The final output is (tone_1_fullscale * scale_1) + (tone_2_fullscale * scale_2). NOT-APPLICABLE if DDS_DISABLE is set (0x1). |
||
0x103 + 0x16*n |
0x40c + 0x58*n |
CHAN_CNTRLn_4 |
DAC Channel Control & Status (channel - 0) Where n is from 0 to 15. |
|||
[31:16] |
DDS_INIT_2 |
RW |
0x0000 |
The DDS phase initialization for tone 2. Sets the initial phase offset of the tone. If DDS_PHASE_DW is greater than 16(from CHAN_CNTRL_1), the phase init for tone 2 is extended in CHAN_CNTRL_10. NOT-APPLICABLE if DDS_DISABLE is set (0x1). |
||
[15:0] |
DDS_INCR_2 |
RW |
0x0000 |
Sets the frequency of the phase accumulator. Its value can be calculated by \(INCR = (f_{out} * 2^{16}) * clkratio / f_{if}\); where f_out is the generated output frequency, and f_if is the frequency of the digital interface, and clock_ratio is the ratio between the sampling clock and the interface clock. If DDS_PHASE_DW is greater than 16(from CHAN_CNTRL_1), the phase increment for tone 2 is extended in CHAN_CNTRL_10. NOT-APPLICABLE if DDS_DISABLE is set (0x1). |
||
0x104 + 0x16*n |
0x410 + 0x58*n |
CHAN_CNTRLn_5 |
DAC Channel Control & Status (channel - 0) Where n is from 0 to 15. |
|||
[31:16] |
DDS_PATT_2 |
RW |
0x0000 |
The DDS data pattern for this channel. |
||
[15:0] |
DDS_PATT_1 |
RW |
0x0000 |
The DDS data pattern for this channel. |
||
0x105 + 0x16*n |
0x414 + 0x58*n |
CHAN_CNTRLn_6 |
DAC Channel Control & Status (channel - 0) Where n is from 0 to 15. |
|||
[2] |
IQCOR_ENB |
RW |
0x0 |
if set, enables IQ correction. NOT-APPLICABLE if DAC_DP_DISABLE is set (0x1). |
||
[1] |
DAC_LB_OWR |
RW |
0x0 |
If set, forces DAC_DDS_SEL to 0x8, loopback If DAC_LB_OWR and DAC_PN_OWR are both set, they are ignored |
||
[0] |
DAC_PN_OWR |
RW |
0x0 |
IF set, forces DAC_DDS_SEL to 0x09, device specific pnX If DAC_LB_OWR and DAC_PN_OWR are both set, they are ignored |
||
0x106 + 0x16*n |
0x418 + 0x58*n |
CHAN_CNTRLn_7 |
DAC Channel Control & Status (channel - 0) Where n is from 0 to 15. |
|||
[3:0] |
DAC_DDS_SEL |
RW |
0x0 |
Select internal data sources (available only if the DAC supports it).
|
||
0x107 + 0x16*n |
0x41c + 0x58*n |
CHAN_CNTRLn_8 |
DAC Channel Control & Status (channel - 0) Where n is from 0 to 15. |
|||
[31:16] |
IQCOR_COEFF_1 |
RW |
0x0000 |
IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the scale value and the format is 1.1.14 (sign, integer and fractional bits). If matrix multiplication is used, this is the channel I coefficient and the format is 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1). |
||
[15:0] |
IQCOR_COEFF_2 |
RW |
0x0000 |
IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the offset value and the format is 2’s complement. If matrix multiplication is used, this is the channel Q coefficient and the format is 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1). |
||
0x108 + 0x16*n |
0x420 + 0x58*n |
USR_CNTRLn_3 |
DAC Channel Control & Status (channel - 0) Where n is from 0 to 15. |
|||
[25] |
USR_DATATYPE_BE |
RW |
0x0 |
The user data type format- if set, indicates big endian (default is little endian). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1). |
||
[24] |
USR_DATATYPE_SIGNED |
RW |
0x0 |
The user data type format- if set, indicates signed (2’s complement) data (default is unsigned). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1). |
||
[23:16] |
USR_DATATYPE_SHIFT |
RW |
0x00 |
The user data type format- the amount of right shift for actual samples within the total number of bits. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1). |
||
[15:8] |
USR_DATATYPE_TOTAL_BITS |
RW |
0x00 |
The user data type format- number of total bits used for a sample. The total number of bits must be an integer multiple of 8 (byte aligned). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1). |
||
[7:0] |
USR_DATATYPE_BITS |
RW |
0x00 |
The user data type format- number of bits in a sample. This indicates the actual sample data bits. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1). |
||
0x109 + 0x16*n |
0x424 + 0x58*n |
USR_CNTRLn_4 |
DAC Channel Control & Status (channel - 0) Where n is from 0 to 15. |
|||
[31:16] |
USR_INTERPOLATION_M |
RW |
0x0000 |
This holds the user interpolation M value of the channel that is currently being selected on the multiplexer above. The total interpolation factor is of the form M/N. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1). |
||
[15:0] |
USR_INTERPOLATION_N |
RW |
0x0000 |
This holds the user interpolation N value of the channel that is currently being selected on the multiplexer above. The total interpolation factor is of the form M/N. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1). |
||
0x10a + 0x16*n |
0x428 + 0x58*n |
USR_CNTRLn_5 |
DAC Channel Control & Status (channel - 0) Where n is from 0 to 15. |
|||
[0] |
DAC_IQ_MODE |
RW |
0x0 |
Enable complex mode. In this mode the driven data to the DAC must be a sequence of I and Q sample pairs. |
||
[1] |
DAC_IQ_SWAP |
RW |
0x0 |
Allows IQ swapping in complex mode. Only takes effect if complex mode is enabled. |
||
0x10b + 0x16*n |
0x42c + 0x58*n |
CHAN_CNTRLn_9 |
DAC Channel Control & Status (channel - 0) Where n is from 0 to 15. |
|||
[31:16] |
DDS_INIT_1_EXTENDED |
RW |
0x0000 |
The extended DDS phase initialization for tone 1. Sets the initial phase offset of the tone. The extended init(phase) value should be calculated according to DDS_PHASE_DW value from CHAN_CNTRL_1 NOT-APPLICABLE if DDS_DISABLE is set (0x1). |
||
[15:0] |
DDS_INCR_1_EXTENDED |
RW |
0x0000 |
Sets the frequency of tone 1’s phase accumulator. Its value can be calculated by \(INCR = (f_{out} * 2^{phaseDW}) * clkratio / f_{if}\); Where f_out is the generated output frequency, DDS_PHASE_DW value can be found in CHAN_CNTRL_1 in case DDS_PHASE_DW is not 16, f_if is the frequency of the digital interface, and clock_ratio is the ratio between the sampling clock and the interface clock. NOT-APPLICABLE if DDS_DISABLE is set (0x1). |
||
0x10c + 0x16*n |
0x430 + 0x58*n |
CHAN_CNTRLn_10 |
DAC Channel Control & Status (channel - 0) Where n is from 0 to 15. |
|||
[31:16] |
DDS_INIT_2_EXTENDED |
RW |
0x0000 |
The extended DDS phase initialization for tone 2. Sets the initial phase offset of the tone. The extended init(phase) value should be calculated according to DDS_PHASE_DW value from CHAN_CNTRL_2 NOT-APPLICABLE if DDS_DISABLE is set (0x1). |
||
[15:0] |
DDS_INCR_2_EXTENDED |
RW |
0x0000 |
Sets the frequency of tone 2’s phase accumulator. Its value can be calculated by \(INCR = (f_{out} * 2^{phaseDW}) * clkratio / f_{if}\); Where f_out is the generated output frequency, DDS_PHASE_DW value can be found in CHAN_CNTRL_2 in case DDS_PHASE_DW is not 16, f_if is the frequency of the digital interface, and clock_ratio is the ratio between the sampling clock and the interface clock. NOT-APPLICABLE if DDS_DISABLE is set (0x1). |
DWORD |
BYTE |
Reg Name |
Description |
|||
---|---|---|---|---|---|---|
BITS |
Field Name |
Type |
Default Value |
Description |
||
0x10 |
0x40 |
TDD_CONTROL_0 |
TDD Control & Status |
|||
[5] |
TDD_GATED_TX_DMAPATH |
RW |
0x0 |
If this bit is set, the core requests data from the TX DMA, just when the data path is active. Otherwise will requests continuously on the adjusted rate. The purpose of this feature is to facilitate debug. This bit must be SET to preserve data integrity. |
||
[4] |
TDD_GATED_RX_DMAPATH |
RW |
0x0 |
If this bit is set, the core provides data for the RX DMA, just when the data path is active. Otherwise will provides continuously on the adjusted rate. The purpose of this feature is to facilitate debug. This bit must be SET to preserve data integrity. |
||
[3] |
TDD_TXONLY |
RW |
0x0 |
If this bit is set- the TDD controller ignores all the TX_* timing registers below and assumes continuous receive operation within a frame. |
||
[2] |
TDD_RXONLY |
RW |
0x0 |
If this bit is set- the TDD controller ignores all the RX_* timing registers below and assumes continuous transmit operation within a frame. |
||
[1] |
TDD_SECONDARY |
RW |
0x0 |
Enable the secondary transmit/receive on the active frame. If this bit is clear - the controller only uses the _1 timing registers below. If this bit is set - the controller uses the _1 and _2 timing registers below. |
||
[0] |
TDD_ENABLE |
RW |
0x0 |
If set, enables the TDD controller- software must set this bit after programming all the registers that controls the tdd timing. Any device settings needs to be done (for example bring the AD9361 to the alert state) prior to to setting this bit. The controller keeps the frame counters in reset if this bit is reset. A 0 to 1 transition in this bit starts the frame counter and tdd mode of operation. |
||
0x11 |
0x44 |
TDD_CONTROL_1 |
TDD Control & Status |
|||
[7:0] |
TDD_BURST_COUNT |
RW |
0x00 |
If set to 0x0 and enabled (TDD_ENABLE is set) - the controller operates in TDD mode as long as the TDD_ENABLE bit is set. If set to a non-zero value, the controller operates for the set number of frames and stops. |
||
0x12 |
0x48 |
TDD_CONTROL_2 |
TDD Control & Status |
|||
[23:0] |
TDD_COUNTER_INIT |
RW |
0x000000 |
The controller sets the frame counter to this value when starting TDD operation. This is the starting offset value for the TDD frame counter. |
||
0x13 |
0x4c |
TDD_FRAME_LENGTH |
TDD Control & Status |
|||
[23:0] |
TDD_FRAME_LENGTH |
RW |
0x000000 |
The frame length is the terminal count for the 10ms counter running at the digital interface clock- as an example for a 245.76MHz clock it is 0x258000. |
||
0x14 |
0x50 |
TDD_SYNC_TERMINAL_TYPE |
TDD Control & Status |
|||
[0] |
TDD_SYNC_TERMINAL_TYPE |
RW |
0x0 |
Set this bit, if the current terminal will generate the syncronization pulse, reset otherwise. |
||
0x18 |
0x60 |
TDD_STATUS |
TDD Control & Status |
|||
[0] |
TDD_RXTX_VCO_OVERLAP |
RO |
0x0 |
This bit is asserted, if exist a time interval when both the TX and RX VCOs are powered up. |
||
[1] |
TDD_RXTX_RF_OVERLAP |
RO |
0x0 |
This bit is asserted, if exist a time interval when both the TX and RX RF datapath are powered up. |
||
0x20 |
0x80 |
TDD_VCO_RX_ON_1 |
TDD Control & Status |
|||
[23:0] |
TDD_VCO_RX_ON_1 |
RW |
0x000000 |
Defines the offset (from frame count equal zero), when the RX VCO powers up at the first time. The controller enables the receive VCO, when the frame count reaches this value. The VCO may have to be enabled before data can be received. The user needs to make sure, that the RF device is in a state, from where this operation is valid. |
||
0x21 |
0x84 |
TDD_VCO_RX_OFF_1 |
TDD Control & Status |
|||
[23:0] |
TDD_VCO_RX_OFF_1 |
RW |
0x000000 |
Defines the offset (from frame count equal zero), when the RX VCO powers down at the first time. The controller disables the receive VCO, when the frame count reaches this value. The user needs to make sure, that the RF device is in a state, from where this operation is valid. |
||
0x22 |
0x88 |
TDD_VCO_TX_ON_1 |
TDD Control & Status |
|||
[23:0] |
TDD_VCO_TX_ON_1 |
RW |
0x000000 |
Defines the offset (from frame count equal zero), when the TX VCO powers up at the first time. The controller enables the transmit VCO, when the frame count reaches this value. The user needs to make sure, that the RF device is in a state, from where this operation is valid. |
||
0x23 |
0x8c |
TDD_VCO_TX_OFF_1 |
TDD Control & Status |
|||
[23:0] |
TDD_VCO_TX_OFF_1 |
RW |
0x000000 |
Defines the offset (from frame count equal zero), when the TX VCO powers down at the first time. The controller disables the transmit VCO when the frame count reaches this value. The user needs to make sure, that the RF device is in a state, from where this operation is valid. |
||
0x24 |
0x90 |
TDD_RX_ON_1 |
TDD Control & Status |
|||
[23:0] |
TDD_RX_ON_1 |
RW |
0x000000 |
Defines the offset (from frame count equal zero), when the RX data path is activated at the first time. The controller enables the receive chain when the frame count reaches this value. The user needs to make sure, that the RF device is in a state, from where this operation is valid. |
||
0x25 |
0x94 |
TDD_RX_OFF_1 |
TDD Control & Status |
|||
[23:0] |
TDD_RX_OFF_1 |
RW |
0x000000 |
Defines the offset (from frame count equal zero), when the RX data path is deactivated the first time. The controller disables the receive chain when the frame count reaches this value. The user needs to make sure, that the RF device is in a state, from where this operation is valid. |
||
0x26 |
0x98 |
TDD_TX_ON_1 |
TDD Control & Status |
|||
[23:0] |
TDD_TX_ON_1 |
RW |
0x000000 |
Defines the offset (from frame count equal zero), when the TX data path is activated at the first time. The controller enables the transmit chain, when the frame count reaches this value. This register and the TX_DP_ON register controls the delay between the data path being activated and the time to actually push the transmit data through the transmit chain in the device. |
||
0x27 |
0x9c |
TDD_TX_OFF_1 |
TDD Control & Status |
|||
[23:0] |
TDD_TX_OFF_1 |
RW |
0x000000 |
Defines the offset (from frame count equal zero), when the TX data path is deactivated at the first time. The controller disables the transmit chain, when the frame count reaches this value. This register and the TX_DP_OFF register controls the delay between the data path being deactivated and the time to actually stop transmitting data through the transmit chain in the device. |
||
0x28 |
0xa0 |
TDD_RX_DP_ON_1 |
TDD Control & Status |
|||
[23:0] |
TDD_RX_DP_ON_1 |
RW |
0x000000 |
Defines the offset (from frame count equal zero), when the controller starts to accept data from the digital interface for receive. |
||
0x29 |
0xa4 |
TDD_RX_DP_OFF_1 |
TDD Control & Status |
|||
[23:0] |
TDD_RX_DP_OFF_1 |
RW |
0x000000 |
Defines the offset (from frame count equal zero), when the controller stops to accept data from the digital interface for receive. |
||
0x2a |
0xa8 |
TDD_TX_DP_ON_1 |
TDD Control & Status |
|||
[23:0] |
TDD_TX_DP_ON_1 |
RW |
0x000000 |
Defines the offset (from frame count equal zero), when the controller starts to request data from the system memory for transmit. The data rate is controlled by the TDD controller. |
||
0x2b |
0xac |
TDD_TX_DP_OFF_1 |
TDD Control & Status |
|||
[23:0] |
TDD_TX_DP_OFF_1 |
RW |
0x000000 |
Defines the offset (from frame count equal zero), when the controller stop requesting data from the system memory for transmit. |
||
0x30 |
0xc0 |
TDD_VCO_RX_ON_2 |
TDD Control & Status |
|||
[23:0] |
TDD_VCO_RX_ON_2 |
RW |
0x000000 |
The secondary pointer for VCO_RX_ON. |
||
0x31 |
0xc4 |
TDD_VCO_RX_OFF_2 |
TDD Control & Status |
|||
[23:0] |
TDD_VCO_RX_OFF_2 |
RW |
0x000000 |
The secondary pointer for VCO_RX_OFF. |
||
0x32 |
0xc8 |
TDD_VCO_TX_ON_2 |
TDD Control & Status |
|||
[23:0] |
TDD_VCO_TX_ON_2 |
RW |
0x000000 |
The secondary pointer for VCO_TX_ON. |
||
0x33 |
0xcc |
TDD_VCO_TX_OFF_2 |
TDD Control & Status |
|||
[23:0] |
TDD_VCO_TX_OFF_2 |
RW |
0x000000 |
The secondary pointer for VCO_TX_OFF. |
||
0x34 |
0xd0 |
TDD_RX_ON_2 |
TDD Control & Status |
|||
[23:0] |
TDD_RX_ON_2 |
RW |
0x000000 |
The secondary pointer for RX_ON. |
||
0x35 |
0xd4 |
TDD_RX_OFF_2 |
TDD Control & Status |
|||
[23:0] |
TDD_RX_OFF_2 |
RW |
0x000000 |
The secondary pointer for RX_OFF. |
||
0x36 |
0xd8 |
TDD_TX_ON_2 |
TDD Control & Status |
|||
[23:0] |
TDD_TX_ON_2 |
RW |
0x000000 |
The secondary pointer for TX_ON. |
||
0x37 |
0xdc |
TDD_TX_OFF_2 |
TDD Control & Status |
|||
[23:0] |
TDD_TX_OFF_2 |
RW |
0x000000 |
The secondary pointer for TX_OFF. |
||
0x38 |
0xe0 |
TDD_RX_DP_ON_2 |
TDD Control & Status |
|||
[23:0] |
TDD_RX_DP_ON_2 |
RW |
0x000000 |
The secondary pointer for RX_DP_ON. |
||
0x39 |
0xe4 |
TDD_RX_DP_OFF_2 |
TDD Control & Status |
|||
[23:0] |
TDD_RX_DP_OFF_2 |
RW |
0x000000 |
The secondary pointer for RX_DP_OFF. |
||
0x3a |
0xe8 |
TDD_TX_DP_ON_2 |
TDD Control & Status |
|||
[23:0] |
TDD_TX_DP_ON_2 |
RW |
0x000000 |
The secondary pointer for TX_DP_ON. |
||
0x3b |
0xec |
TDD_TX_DP_OFF_2 |
TDD Control & Status |
|||
[23:0] |
TDD_TX_DP_OFF_2 |
RW |
0x000000 |
The secondary pointer for TX_DP_OFF. |
References
HDL IP core at library/axi_adrv9001
HDL project at projects/adrv9001
HDL project documentation at ADRV9001 HDL Project
No-OS driver at drivers/rf-transceiver/navassa/devices/adrv9001
Linux driver at drivers/iio/adc/navassa