MAX32690 Peripheral Driver API
Peripheral Driver API for the MAX32690
can_regs.h
Go to the documentation of this file.
1
8/******************************************************************************
9 *
10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by
11 * Analog Devices, Inc.),
12 * Copyright (C) 2023-2024 Analog Devices, Inc.
13 *
14 * Licensed under the Apache License, Version 2.0 (the "License");
15 * you may not use this file except in compliance with the License.
16 * You may obtain a copy of the License at
17 *
18 * http://www.apache.org/licenses/LICENSE-2.0
19 *
20 * Unless required by applicable law or agreed to in writing, software
21 * distributed under the License is distributed on an "AS IS" BASIS,
22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 * See the License for the specific language governing permissions and
24 * limitations under the License.
25 *
26 ******************************************************************************/
27
28#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32690_INCLUDE_CAN_REGS_H_
29#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32690_INCLUDE_CAN_REGS_H_
30
31/* **** Includes **** */
32#include <stdint.h>
33
34#ifdef __cplusplus
35extern "C" {
36#endif
37
38#if defined (__ICCARM__)
39 #pragma system_include
40#endif
41
42#if defined (__CC_ARM)
43 #pragma anon_unions
44#endif
46/*
47 If types are not defined elsewhere (CMSIS) define them here
48*/
49#ifndef __IO
50#define __IO volatile
51#endif
52#ifndef __I
53#define __I volatile const
54#endif
55#ifndef __O
56#define __O volatile
57#endif
58#ifndef __R
59#define __R volatile const
60#endif
62
63/* **** Definitions **** */
64
76typedef struct {
77 __IO uint8_t mode;
78 __IO uint8_t cmd;
79 __I uint8_t stat;
80 __IO uint8_t intfl;
81 __IO uint8_t inten;
82 __IO uint8_t rmc;
83 __IO uint8_t bustim0;
84 __IO uint8_t bustim1;
85 union {
86 __IO uint32_t txfifo32;
87 __IO uint16_t txfifo16[2];
88 __IO uint8_t txfifo8[4];
89 };
90 union {
91 __I uint32_t rxfifo32;
92 __I uint16_t rxfifo16[2];
93 __I uint8_t rxfifo8[4];
94 };
95 union {
96 __IO uint32_t acr32;
97 __IO uint16_t acr16[2];
98 __IO uint8_t acr8[4];
99 };
100 union {
101 __IO uint32_t amr32;
102 __IO uint16_t amr16[2];
103 __IO uint8_t amr8[4];
104 };
105 __I uint8_t ecc;
106 __IO uint8_t rxerr;
107 __IO uint8_t txerr;
108 __I uint8_t alc;
109 __IO uint32_t nbt;
110 __IO uint32_t dbt_sspp;
111 __IO uint8_t fdctrl;
112 __I uint8_t fdstat;
113 __I uint8_t dperr;
114 __I uint8_t aperr;
115 __IO uint8_t test;
116 __IO uint8_t wupclkdiv;
117 __IO uint16_t wupft;
118 __IO uint32_t wupet;
119 __IO uint16_t rxdcnt;
120 __IO uint8_t txscnt;
121 __IO uint8_t txdecmp;
122 __IO uint8_t eintfl;
123 __IO uint8_t einten;
124 __IO uint16_t rxto;
125} mxc_can_regs_t;
126
127/* Register offsets for module CAN */
134#define MXC_R_CAN_MODE ((uint32_t)0x00000000UL)
135#define MXC_R_CAN_CMD ((uint32_t)0x00000001UL)
136#define MXC_R_CAN_STAT ((uint32_t)0x00000002UL)
137#define MXC_R_CAN_INTFL ((uint32_t)0x00000003UL)
138#define MXC_R_CAN_INTEN ((uint32_t)0x00000004UL)
139#define MXC_R_CAN_RMC ((uint32_t)0x00000005UL)
140#define MXC_R_CAN_BUSTIM0 ((uint32_t)0x00000006UL)
141#define MXC_R_CAN_BUSTIM1 ((uint32_t)0x00000007UL)
142#define MXC_R_CAN_TXFIFO32 ((uint32_t)0x00000008UL)
143#define MXC_R_CAN_TXFIFO16 ((uint32_t)0x00000008UL)
144#define MXC_R_CAN_TXFIFO8 ((uint32_t)0x00000008UL)
145#define MXC_R_CAN_RXFIFO32 ((uint32_t)0x0000000CUL)
146#define MXC_R_CAN_RXFIFO16 ((uint32_t)0x0000000CUL)
147#define MXC_R_CAN_RXFIFO8 ((uint32_t)0x0000000CUL)
148#define MXC_R_CAN_ACR32 ((uint32_t)0x00000010UL)
149#define MXC_R_CAN_ACR16 ((uint32_t)0x00000010UL)
150#define MXC_R_CAN_ACR8 ((uint32_t)0x00000010UL)
151#define MXC_R_CAN_AMR32 ((uint32_t)0x00000014UL)
152#define MXC_R_CAN_AMR16 ((uint32_t)0x00000014UL)
153#define MXC_R_CAN_AMR8 ((uint32_t)0x00000014UL)
154#define MXC_R_CAN_ECC ((uint32_t)0x00000018UL)
155#define MXC_R_CAN_RXERR ((uint32_t)0x00000019UL)
156#define MXC_R_CAN_TXERR ((uint32_t)0x0000001AUL)
157#define MXC_R_CAN_ALC ((uint32_t)0x0000001BUL)
158#define MXC_R_CAN_NBT ((uint32_t)0x0000001CUL)
159#define MXC_R_CAN_DBT_SSPP ((uint32_t)0x00000020UL)
160#define MXC_R_CAN_FDCTRL ((uint32_t)0x00000024UL)
161#define MXC_R_CAN_FDSTAT ((uint32_t)0x00000025UL)
162#define MXC_R_CAN_DPERR ((uint32_t)0x00000026UL)
163#define MXC_R_CAN_APERR ((uint32_t)0x00000027UL)
164#define MXC_R_CAN_TEST ((uint32_t)0x00000028UL)
165#define MXC_R_CAN_WUPCLKDIV ((uint32_t)0x00000029UL)
166#define MXC_R_CAN_WUPFT ((uint32_t)0x0000002AUL)
167#define MXC_R_CAN_WUPET ((uint32_t)0x0000002CUL)
168#define MXC_R_CAN_RXDCNT ((uint32_t)0x00000030UL)
169#define MXC_R_CAN_TXSCNT ((uint32_t)0x00000032UL)
170#define MXC_R_CAN_TXDECMP ((uint32_t)0x00000033UL)
171#define MXC_R_CAN_EINTFL ((uint32_t)0x00000034UL)
172#define MXC_R_CAN_EINTEN ((uint32_t)0x00000035UL)
173#define MXC_R_CAN_RXTO ((uint32_t)0x00000036UL)
182#define MXC_F_CAN_MODE_AFM_POS 0
183#define MXC_F_CAN_MODE_AFM ((uint8_t)(0x1UL << MXC_F_CAN_MODE_AFM_POS))
185#define MXC_F_CAN_MODE_LOM_POS 1
186#define MXC_F_CAN_MODE_LOM ((uint8_t)(0x1UL << MXC_F_CAN_MODE_LOM_POS))
188#define MXC_F_CAN_MODE_RST_POS 2
189#define MXC_F_CAN_MODE_RST ((uint8_t)(0x1UL << MXC_F_CAN_MODE_RST_POS))
191#define MXC_F_CAN_MODE_RXTRIG_POS 3
192#define MXC_F_CAN_MODE_RXTRIG ((uint8_t)(0x7UL << MXC_F_CAN_MODE_RXTRIG_POS))
193#define MXC_V_CAN_MODE_RXTRIG_1W ((uint8_t)0x0UL)
194#define MXC_S_CAN_MODE_RXTRIG_1W (MXC_V_CAN_MODE_RXTRIG_1W << MXC_F_CAN_MODE_RXTRIG_POS)
195#define MXC_V_CAN_MODE_RXTRIG_4W ((uint8_t)0x1UL)
196#define MXC_S_CAN_MODE_RXTRIG_4W (MXC_V_CAN_MODE_RXTRIG_4W << MXC_F_CAN_MODE_RXTRIG_POS)
197#define MXC_V_CAN_MODE_RXTRIG_8W ((uint8_t)0x2UL)
198#define MXC_S_CAN_MODE_RXTRIG_8W (MXC_V_CAN_MODE_RXTRIG_8W << MXC_F_CAN_MODE_RXTRIG_POS)
199#define MXC_V_CAN_MODE_RXTRIG_16W ((uint8_t)0x3UL)
200#define MXC_S_CAN_MODE_RXTRIG_16W (MXC_V_CAN_MODE_RXTRIG_16W << MXC_F_CAN_MODE_RXTRIG_POS)
201#define MXC_V_CAN_MODE_RXTRIG_32W ((uint8_t)0x4UL)
202#define MXC_S_CAN_MODE_RXTRIG_32W (MXC_V_CAN_MODE_RXTRIG_32W << MXC_F_CAN_MODE_RXTRIG_POS)
203#define MXC_V_CAN_MODE_RXTRIG_64W ((uint8_t)0x5UL)
204#define MXC_S_CAN_MODE_RXTRIG_64W (MXC_V_CAN_MODE_RXTRIG_64W << MXC_F_CAN_MODE_RXTRIG_POS)
206#define MXC_F_CAN_MODE_DMA_POS 6
207#define MXC_F_CAN_MODE_DMA ((uint8_t)(0x1UL << MXC_F_CAN_MODE_DMA_POS))
209#define MXC_F_CAN_MODE_SLP_POS 7
210#define MXC_F_CAN_MODE_SLP ((uint8_t)(0x1UL << MXC_F_CAN_MODE_SLP_POS))
220#define MXC_F_CAN_CMD_ABORT_POS 1
221#define MXC_F_CAN_CMD_ABORT ((uint8_t)(0x1UL << MXC_F_CAN_CMD_ABORT_POS))
223#define MXC_F_CAN_CMD_TXREQ_POS 2
224#define MXC_F_CAN_CMD_TXREQ ((uint8_t)(0x1UL << MXC_F_CAN_CMD_TXREQ_POS))
234#define MXC_F_CAN_STAT_BUS_OFF_POS 0
235#define MXC_F_CAN_STAT_BUS_OFF ((uint8_t)(0x1UL << MXC_F_CAN_STAT_BUS_OFF_POS))
237#define MXC_F_CAN_STAT_ERR_POS 1
238#define MXC_F_CAN_STAT_ERR ((uint8_t)(0x1UL << MXC_F_CAN_STAT_ERR_POS))
240#define MXC_F_CAN_STAT_TX_POS 2
241#define MXC_F_CAN_STAT_TX ((uint8_t)(0x1UL << MXC_F_CAN_STAT_TX_POS))
243#define MXC_F_CAN_STAT_RX_POS 3
244#define MXC_F_CAN_STAT_RX ((uint8_t)(0x1UL << MXC_F_CAN_STAT_RX_POS))
246#define MXC_F_CAN_STAT_TXBUF_POS 5
247#define MXC_F_CAN_STAT_TXBUF ((uint8_t)(0x1UL << MXC_F_CAN_STAT_TXBUF_POS))
249#define MXC_F_CAN_STAT_DOR_POS 6
250#define MXC_F_CAN_STAT_DOR ((uint8_t)(0x1UL << MXC_F_CAN_STAT_DOR_POS))
252#define MXC_F_CAN_STAT_RXBUF_POS 7
253#define MXC_F_CAN_STAT_RXBUF ((uint8_t)(0x1UL << MXC_F_CAN_STAT_RXBUF_POS))
263#define MXC_F_CAN_INTFL_DOR_POS 0
264#define MXC_F_CAN_INTFL_DOR ((uint8_t)(0x1UL << MXC_F_CAN_INTFL_DOR_POS))
266#define MXC_F_CAN_INTFL_BERR_POS 1
267#define MXC_F_CAN_INTFL_BERR ((uint8_t)(0x1UL << MXC_F_CAN_INTFL_BERR_POS))
269#define MXC_F_CAN_INTFL_TX_POS 2
270#define MXC_F_CAN_INTFL_TX ((uint8_t)(0x1UL << MXC_F_CAN_INTFL_TX_POS))
272#define MXC_F_CAN_INTFL_RX_POS 3
273#define MXC_F_CAN_INTFL_RX ((uint8_t)(0x1UL << MXC_F_CAN_INTFL_RX_POS))
275#define MXC_F_CAN_INTFL_ERPSV_POS 4
276#define MXC_F_CAN_INTFL_ERPSV ((uint8_t)(0x1UL << MXC_F_CAN_INTFL_ERPSV_POS))
278#define MXC_F_CAN_INTFL_ERWARN_POS 5
279#define MXC_F_CAN_INTFL_ERWARN ((uint8_t)(0x1UL << MXC_F_CAN_INTFL_ERWARN_POS))
281#define MXC_F_CAN_INTFL_AL_POS 6
282#define MXC_F_CAN_INTFL_AL ((uint8_t)(0x1UL << MXC_F_CAN_INTFL_AL_POS))
284#define MXC_F_CAN_INTFL_WU_POS 7
285#define MXC_F_CAN_INTFL_WU ((uint8_t)(0x1UL << MXC_F_CAN_INTFL_WU_POS))
295#define MXC_F_CAN_INTEN_DOR_POS 0
296#define MXC_F_CAN_INTEN_DOR ((uint8_t)(0x1UL << MXC_F_CAN_INTEN_DOR_POS))
298#define MXC_F_CAN_INTEN_BERR_POS 1
299#define MXC_F_CAN_INTEN_BERR ((uint8_t)(0x1UL << MXC_F_CAN_INTEN_BERR_POS))
301#define MXC_F_CAN_INTEN_TX_POS 2
302#define MXC_F_CAN_INTEN_TX ((uint8_t)(0x1UL << MXC_F_CAN_INTEN_TX_POS))
304#define MXC_F_CAN_INTEN_RX_POS 3
305#define MXC_F_CAN_INTEN_RX ((uint8_t)(0x1UL << MXC_F_CAN_INTEN_RX_POS))
307#define MXC_F_CAN_INTEN_ERPSV_POS 4
308#define MXC_F_CAN_INTEN_ERPSV ((uint8_t)(0x1UL << MXC_F_CAN_INTEN_ERPSV_POS))
310#define MXC_F_CAN_INTEN_ERWARN_POS 5
311#define MXC_F_CAN_INTEN_ERWARN ((uint8_t)(0x1UL << MXC_F_CAN_INTEN_ERWARN_POS))
313#define MXC_F_CAN_INTEN_AL_POS 6
314#define MXC_F_CAN_INTEN_AL ((uint8_t)(0x1UL << MXC_F_CAN_INTEN_AL_POS))
316#define MXC_F_CAN_INTEN_WU_POS 7
317#define MXC_F_CAN_INTEN_WU ((uint8_t)(0x1UL << MXC_F_CAN_INTEN_WU_POS))
327#define MXC_F_CAN_RMC_NUM_MSGS_POS 0
328#define MXC_F_CAN_RMC_NUM_MSGS ((uint8_t)(0x1FUL << MXC_F_CAN_RMC_NUM_MSGS_POS))
338#define MXC_F_CAN_BUSTIM0_BR_CLKDIV_POS 0
339#define MXC_F_CAN_BUSTIM0_BR_CLKDIV ((uint8_t)(0x3FUL << MXC_F_CAN_BUSTIM0_BR_CLKDIV_POS))
341#define MXC_F_CAN_BUSTIM0_SJW_POS 6
342#define MXC_F_CAN_BUSTIM0_SJW ((uint8_t)(0x3UL << MXC_F_CAN_BUSTIM0_SJW_POS))
352#define MXC_F_CAN_BUSTIM1_TSEG1_POS 0
353#define MXC_F_CAN_BUSTIM1_TSEG1 ((uint8_t)(0xFUL << MXC_F_CAN_BUSTIM1_TSEG1_POS))
355#define MXC_F_CAN_BUSTIM1_TSEG2_POS 4
356#define MXC_F_CAN_BUSTIM1_TSEG2 ((uint8_t)(0x7UL << MXC_F_CAN_BUSTIM1_TSEG2_POS))
358#define MXC_F_CAN_BUSTIM1_SAM_POS 7
359#define MXC_F_CAN_BUSTIM1_SAM ((uint8_t)(0x1UL << MXC_F_CAN_BUSTIM1_SAM_POS))
369#define MXC_F_CAN_TXFIFO32_DATA_POS 0
370#define MXC_F_CAN_TXFIFO32_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_CAN_TXFIFO32_DATA_POS))
380#define MXC_F_CAN_TXFIFO16_DATA_POS 0
381#define MXC_F_CAN_TXFIFO16_DATA ((uint16_t)(0xFFFFUL << MXC_F_CAN_TXFIFO16_DATA_POS))
391#define MXC_F_CAN_TXFIFO8_DATA_POS 0
392#define MXC_F_CAN_TXFIFO8_DATA ((uint8_t)(0xFFUL << MXC_F_CAN_TXFIFO8_DATA_POS))
402#define MXC_F_CAN_RXFIFO32_DATA_POS 0
403#define MXC_F_CAN_RXFIFO32_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_CAN_RXFIFO32_DATA_POS))
413#define MXC_F_CAN_RXFIFO16_DATA_POS 0
414#define MXC_F_CAN_RXFIFO16_DATA ((uint16_t)(0xFFFFUL << MXC_F_CAN_RXFIFO16_DATA_POS))
424#define MXC_F_CAN_RXFIFO8_DATA_POS 0
425#define MXC_F_CAN_RXFIFO8_DATA ((uint8_t)(0xFFUL << MXC_F_CAN_RXFIFO8_DATA_POS))
435#define MXC_F_CAN_ACR32_ACR_POS 0
436#define MXC_F_CAN_ACR32_ACR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CAN_ACR32_ACR_POS))
446#define MXC_F_CAN_ACR16_ACR_POS 0
447#define MXC_F_CAN_ACR16_ACR ((uint16_t)(0xFFFFUL << MXC_F_CAN_ACR16_ACR_POS))
457#define MXC_F_CAN_ACR8_ACR_POS 0
458#define MXC_F_CAN_ACR8_ACR ((uint8_t)(0xFFUL << MXC_F_CAN_ACR8_ACR_POS))
468#define MXC_F_CAN_AMR32_AMR_POS 0
469#define MXC_F_CAN_AMR32_AMR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CAN_AMR32_AMR_POS))
479#define MXC_F_CAN_AMR16_AMR_POS 0
480#define MXC_F_CAN_AMR16_AMR ((uint16_t)(0xFFFFUL << MXC_F_CAN_AMR16_AMR_POS))
490#define MXC_F_CAN_AMR8_AMR_POS 0
491#define MXC_F_CAN_AMR8_AMR ((uint8_t)(0xFFUL << MXC_F_CAN_AMR8_AMR_POS))
501#define MXC_F_CAN_ECC_BER_POS 0
502#define MXC_F_CAN_ECC_BER ((uint8_t)(0x1UL << MXC_F_CAN_ECC_BER_POS))
504#define MXC_F_CAN_ECC_STFER_POS 1
505#define MXC_F_CAN_ECC_STFER ((uint8_t)(0x1UL << MXC_F_CAN_ECC_STFER_POS))
507#define MXC_F_CAN_ECC_CRCER_POS 2
508#define MXC_F_CAN_ECC_CRCER ((uint8_t)(0x1UL << MXC_F_CAN_ECC_CRCER_POS))
510#define MXC_F_CAN_ECC_FRMER_POS 3
511#define MXC_F_CAN_ECC_FRMER ((uint8_t)(0x1UL << MXC_F_CAN_ECC_FRMER_POS))
513#define MXC_F_CAN_ECC_ACKER_POS 4
514#define MXC_F_CAN_ECC_ACKER ((uint8_t)(0x1UL << MXC_F_CAN_ECC_ACKER_POS))
516#define MXC_F_CAN_ECC_EDIR_POS 5
517#define MXC_F_CAN_ECC_EDIR ((uint8_t)(0x1UL << MXC_F_CAN_ECC_EDIR_POS))
519#define MXC_F_CAN_ECC_TXWRN_POS 6
520#define MXC_F_CAN_ECC_TXWRN ((uint8_t)(0x1UL << MXC_F_CAN_ECC_TXWRN_POS))
522#define MXC_F_CAN_ECC_RXWRN_POS 7
523#define MXC_F_CAN_ECC_RXWRN ((uint8_t)(0x1UL << MXC_F_CAN_ECC_RXWRN_POS))
533#define MXC_F_CAN_RXERR_RXERR_POS 0
534#define MXC_F_CAN_RXERR_RXERR ((uint8_t)(0xFFUL << MXC_F_CAN_RXERR_RXERR_POS))
544#define MXC_F_CAN_TXERR_TXERR_POS 0
545#define MXC_F_CAN_TXERR_TXERR ((uint8_t)(0xFFUL << MXC_F_CAN_TXERR_TXERR_POS))
555#define MXC_F_CAN_ALC_ALC_POS 0
556#define MXC_F_CAN_ALC_ALC ((uint8_t)(0x1FUL << MXC_F_CAN_ALC_ALC_POS))
566#define MXC_F_CAN_NBT_NBRP_POS 0
567#define MXC_F_CAN_NBT_NBRP ((uint32_t)(0x3FFUL << MXC_F_CAN_NBT_NBRP_POS))
569#define MXC_F_CAN_NBT_NSEG1_POS 10
570#define MXC_F_CAN_NBT_NSEG1 ((uint32_t)(0xFFUL << MXC_F_CAN_NBT_NSEG1_POS))
572#define MXC_F_CAN_NBT_NSEG2_POS 18
573#define MXC_F_CAN_NBT_NSEG2 ((uint32_t)(0x7FUL << MXC_F_CAN_NBT_NSEG2_POS))
575#define MXC_F_CAN_NBT_NSJW_POS 25
576#define MXC_F_CAN_NBT_NSJW ((uint32_t)(0x7FUL << MXC_F_CAN_NBT_NSJW_POS))
586#define MXC_F_CAN_DBT_SSPP_DBRP_POS 0
587#define MXC_F_CAN_DBT_SSPP_DBRP ((uint32_t)(0x3FFUL << MXC_F_CAN_DBT_SSPP_DBRP_POS))
589#define MXC_F_CAN_DBT_SSPP_DSEG1_POS 10
590#define MXC_F_CAN_DBT_SSPP_DSEG1 ((uint32_t)(0x3FUL << MXC_F_CAN_DBT_SSPP_DSEG1_POS))
592#define MXC_F_CAN_DBT_SSPP_DSEG2_POS 16
593#define MXC_F_CAN_DBT_SSPP_DSEG2 ((uint32_t)(0xFUL << MXC_F_CAN_DBT_SSPP_DSEG2_POS))
595#define MXC_F_CAN_DBT_SSPP_DSJW_POS 20
596#define MXC_F_CAN_DBT_SSPP_DSJW ((uint32_t)(0xFUL << MXC_F_CAN_DBT_SSPP_DSJW_POS))
598#define MXC_F_CAN_DBT_SSPP_SSPP_POS 24
599#define MXC_F_CAN_DBT_SSPP_SSPP ((uint32_t)(0x7FUL << MXC_F_CAN_DBT_SSPP_SSPP_POS))
609#define MXC_F_CAN_FDCTRL_FDEN_POS 0
610#define MXC_F_CAN_FDCTRL_FDEN ((uint8_t)(0x1UL << MXC_F_CAN_FDCTRL_FDEN_POS))
612#define MXC_F_CAN_FDCTRL_BRSEN_POS 1
613#define MXC_F_CAN_FDCTRL_BRSEN ((uint8_t)(0x1UL << MXC_F_CAN_FDCTRL_BRSEN_POS))
615#define MXC_F_CAN_FDCTRL_EXTBT_POS 2
616#define MXC_F_CAN_FDCTRL_EXTBT ((uint8_t)(0x1UL << MXC_F_CAN_FDCTRL_EXTBT_POS))
618#define MXC_F_CAN_FDCTRL_ISO_POS 3
619#define MXC_F_CAN_FDCTRL_ISO ((uint8_t)(0x1UL << MXC_F_CAN_FDCTRL_ISO_POS))
621#define MXC_F_CAN_FDCTRL_DAR_POS 4
622#define MXC_F_CAN_FDCTRL_DAR ((uint8_t)(0x1UL << MXC_F_CAN_FDCTRL_DAR_POS))
624#define MXC_F_CAN_FDCTRL_REOM_POS 5
625#define MXC_F_CAN_FDCTRL_REOM ((uint8_t)(0x1UL << MXC_F_CAN_FDCTRL_REOM_POS))
627#define MXC_F_CAN_FDCTRL_PED_POS 6
628#define MXC_F_CAN_FDCTRL_PED ((uint8_t)(0x1UL << MXC_F_CAN_FDCTRL_PED_POS))
638#define MXC_F_CAN_FDSTAT_BITERR_POS 0
639#define MXC_F_CAN_FDSTAT_BITERR ((uint8_t)(0x1UL << MXC_F_CAN_FDSTAT_BITERR_POS))
641#define MXC_F_CAN_FDSTAT_CRCERR_POS 1
642#define MXC_F_CAN_FDSTAT_CRCERR ((uint8_t)(0x1UL << MXC_F_CAN_FDSTAT_CRCERR_POS))
644#define MXC_F_CAN_FDSTAT_FRMERR_POS 2
645#define MXC_F_CAN_FDSTAT_FRMERR ((uint8_t)(0x1UL << MXC_F_CAN_FDSTAT_FRMERR_POS))
647#define MXC_F_CAN_FDSTAT_STFERR_POS 3
648#define MXC_F_CAN_FDSTAT_STFERR ((uint8_t)(0x1UL << MXC_F_CAN_FDSTAT_STFERR_POS))
650#define MXC_F_CAN_FDSTAT_PEE_POS 4
651#define MXC_F_CAN_FDSTAT_PEE ((uint8_t)(0x1UL << MXC_F_CAN_FDSTAT_PEE_POS))
653#define MXC_F_CAN_FDSTAT_STATE_POS 6
654#define MXC_F_CAN_FDSTAT_STATE ((uint8_t)(0x3UL << MXC_F_CAN_FDSTAT_STATE_POS))
655#define MXC_V_CAN_FDSTAT_STATE_INT ((uint8_t)0x0UL)
656#define MXC_S_CAN_FDSTAT_STATE_INT (MXC_V_CAN_FDSTAT_STATE_INT << MXC_F_CAN_FDSTAT_STATE_POS)
657#define MXC_V_CAN_FDSTAT_STATE_IDLE ((uint8_t)0x1UL)
658#define MXC_S_CAN_FDSTAT_STATE_IDLE (MXC_V_CAN_FDSTAT_STATE_IDLE << MXC_F_CAN_FDSTAT_STATE_POS)
659#define MXC_V_CAN_FDSTAT_STATE_RX ((uint8_t)0x2UL)
660#define MXC_S_CAN_FDSTAT_STATE_RX (MXC_V_CAN_FDSTAT_STATE_RX << MXC_F_CAN_FDSTAT_STATE_POS)
661#define MXC_V_CAN_FDSTAT_STATE_TX ((uint8_t)0x3UL)
662#define MXC_S_CAN_FDSTAT_STATE_TX (MXC_V_CAN_FDSTAT_STATE_TX << MXC_F_CAN_FDSTAT_STATE_POS)
672#define MXC_F_CAN_DPERR_DPERR_POS 0
673#define MXC_F_CAN_DPERR_DPERR ((uint8_t)(0xFFUL << MXC_F_CAN_DPERR_DPERR_POS))
683#define MXC_F_CAN_APERR_APERR_POS 0
684#define MXC_F_CAN_APERR_APERR ((uint8_t)(0xFFUL << MXC_F_CAN_APERR_APERR_POS))
694#define MXC_F_CAN_TEST_LBEN_POS 0
695#define MXC_F_CAN_TEST_LBEN ((uint8_t)(0x1UL << MXC_F_CAN_TEST_LBEN_POS))
697#define MXC_F_CAN_TEST_TXC_POS 1
698#define MXC_F_CAN_TEST_TXC ((uint8_t)(0x1UL << MXC_F_CAN_TEST_TXC_POS))
708#define MXC_F_CAN_WUPCLKDIV_WUPDIV_POS 0
709#define MXC_F_CAN_WUPCLKDIV_WUPDIV ((uint8_t)(0xFFUL << MXC_F_CAN_WUPCLKDIV_WUPDIV_POS))
719#define MXC_F_CAN_WUPFT_WUPFT_POS 0
720#define MXC_F_CAN_WUPFT_WUPFT ((uint16_t)(0xFFFFUL << MXC_F_CAN_WUPFT_WUPFT_POS))
730#define MXC_F_CAN_WUPET_WUPET_POS 0
731#define MXC_F_CAN_WUPET_WUPET ((uint32_t)(0xFFFFFUL << MXC_F_CAN_WUPET_WUPET_POS))
741#define MXC_F_CAN_RXDCNT_RXDCNT_POS 0
742#define MXC_F_CAN_RXDCNT_RXDCNT ((uint16_t)(0xFFFFUL << MXC_F_CAN_RXDCNT_RXDCNT_POS))
752#define MXC_F_CAN_TXSCNT_TXSCNT_POS 0
753#define MXC_F_CAN_TXSCNT_TXSCNT ((uint8_t)(0xFFUL << MXC_F_CAN_TXSCNT_TXSCNT_POS))
763#define MXC_F_CAN_TXDECMP_TDCO_POS 0
764#define MXC_F_CAN_TXDECMP_TDCO ((uint8_t)(0x7FUL << MXC_F_CAN_TXDECMP_TDCO_POS))
766#define MXC_F_CAN_TXDECMP_TDCEN_POS 7
767#define MXC_F_CAN_TXDECMP_TDCEN ((uint8_t)(0x1UL << MXC_F_CAN_TXDECMP_TDCEN_POS))
777#define MXC_F_CAN_EINTFL_RX_THD_POS 0
778#define MXC_F_CAN_EINTFL_RX_THD ((uint8_t)(0x1UL << MXC_F_CAN_EINTFL_RX_THD_POS))
780#define MXC_F_CAN_EINTFL_RX_TO_POS 1
781#define MXC_F_CAN_EINTFL_RX_TO ((uint8_t)(0x1UL << MXC_F_CAN_EINTFL_RX_TO_POS))
791#define MXC_F_CAN_EINTEN_RX_THD_POS 0
792#define MXC_F_CAN_EINTEN_RX_THD ((uint8_t)(0x1UL << MXC_F_CAN_EINTEN_RX_THD_POS))
794#define MXC_F_CAN_EINTEN_RX_TO_POS 1
795#define MXC_F_CAN_EINTEN_RX_TO ((uint8_t)(0x1UL << MXC_F_CAN_EINTEN_RX_TO_POS))
805#define MXC_F_CAN_RXTO_RX_TO_POS 0
806#define MXC_F_CAN_RXTO_RX_TO ((uint16_t)(0xFFFFUL << MXC_F_CAN_RXTO_RX_TO_POS))
810#ifdef __cplusplus
811}
812#endif
813
814#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32690_INCLUDE_CAN_REGS_H_
mxc_can_regs_t::einten
__IO uint8_t einten
Definition: can_regs.h:123
mxc_can_regs_t::rxfifo32
__I uint32_t rxfifo32
Definition: can_regs.h:91
mxc_can_regs_t::amr32
__IO uint32_t amr32
Definition: can_regs.h:101
mxc_can_regs_t::dbt_sspp
__IO uint32_t dbt_sspp
Definition: can_regs.h:110
mxc_can_regs_t::alc
__I uint8_t alc
Definition: can_regs.h:108
mxc_can_regs_t::test
__IO uint8_t test
Definition: can_regs.h:115
mxc_can_regs_t::mode
__IO uint8_t mode
Definition: can_regs.h:77
mxc_can_regs_t::rxerr
__IO uint8_t rxerr
Definition: can_regs.h:106
mxc_can_regs_t::eintfl
__IO uint8_t eintfl
Definition: can_regs.h:122
mxc_can_regs_t::fdctrl
__IO uint8_t fdctrl
Definition: can_regs.h:111
mxc_can_regs_t::inten
__IO uint8_t inten
Definition: can_regs.h:81
mxc_can_regs_t::stat
__I uint8_t stat
Definition: can_regs.h:79
mxc_can_regs_t::wupft
__IO uint16_t wupft
Definition: can_regs.h:117
mxc_can_regs_t::intfl
__IO uint8_t intfl
Definition: can_regs.h:80
mxc_can_regs_t::bustim1
__IO uint8_t bustim1
Definition: can_regs.h:84
mxc_can_regs_t::wupet
__IO uint32_t wupet
Definition: can_regs.h:118
mxc_can_regs_t::bustim0
__IO uint8_t bustim0
Definition: can_regs.h:83
mxc_can_regs_t::dperr
__I uint8_t dperr
Definition: can_regs.h:113
mxc_can_regs_t::aperr
__I uint8_t aperr
Definition: can_regs.h:114
mxc_can_regs_t::wupclkdiv
__IO uint8_t wupclkdiv
Definition: can_regs.h:116
mxc_can_regs_t::txdecmp
__IO uint8_t txdecmp
Definition: can_regs.h:121
mxc_can_regs_t::rxdcnt
__IO uint16_t rxdcnt
Definition: can_regs.h:119
mxc_can_regs_t::txfifo32
__IO uint32_t txfifo32
Definition: can_regs.h:86
mxc_can_regs_t::rmc
__IO uint8_t rmc
Definition: can_regs.h:82
mxc_can_regs_t::rxto
__IO uint16_t rxto
Definition: can_regs.h:124
mxc_can_regs_t::ecc
__I uint8_t ecc
Definition: can_regs.h:105
mxc_can_regs_t::nbt
__IO uint32_t nbt
Definition: can_regs.h:109
mxc_can_regs_t::cmd
__IO uint8_t cmd
Definition: can_regs.h:78
mxc_can_regs_t::txerr
__IO uint8_t txerr
Definition: can_regs.h:107
mxc_can_regs_t::acr32
__IO uint32_t acr32
Definition: can_regs.h:96
mxc_can_regs_t::txscnt
__IO uint8_t txscnt
Definition: can_regs.h:120
mxc_can_regs_t::fdstat
__I uint8_t fdstat
Definition: can_regs.h:112
mxc_can_regs_t
Definition: can_regs.h:76