|
| #define | MXC_R_CAN_MODE ((uint32_t)0x00000000UL) |
| |
| #define | MXC_R_CAN_CMD ((uint32_t)0x00000001UL) |
| |
| #define | MXC_R_CAN_STAT ((uint32_t)0x00000002UL) |
| |
| #define | MXC_R_CAN_INTFL ((uint32_t)0x00000003UL) |
| |
| #define | MXC_R_CAN_INTEN ((uint32_t)0x00000004UL) |
| |
| #define | MXC_R_CAN_RMC ((uint32_t)0x00000005UL) |
| |
| #define | MXC_R_CAN_BUSTIM0 ((uint32_t)0x00000006UL) |
| |
| #define | MXC_R_CAN_BUSTIM1 ((uint32_t)0x00000007UL) |
| |
| #define | MXC_R_CAN_TXFIFO32 ((uint32_t)0x00000008UL) |
| |
| #define | MXC_R_CAN_TXFIFO16 ((uint32_t)0x00000008UL) |
| |
| #define | MXC_R_CAN_TXFIFO8 ((uint32_t)0x00000008UL) |
| |
| #define | MXC_R_CAN_RXFIFO32 ((uint32_t)0x0000000CUL) |
| |
| #define | MXC_R_CAN_RXFIFO16 ((uint32_t)0x0000000CUL) |
| |
| #define | MXC_R_CAN_RXFIFO8 ((uint32_t)0x0000000CUL) |
| |
| #define | MXC_R_CAN_ACR32 ((uint32_t)0x00000010UL) |
| |
| #define | MXC_R_CAN_ACR16 ((uint32_t)0x00000010UL) |
| |
| #define | MXC_R_CAN_ACR8 ((uint32_t)0x00000010UL) |
| |
| #define | MXC_R_CAN_AMR32 ((uint32_t)0x00000014UL) |
| |
| #define | MXC_R_CAN_AMR16 ((uint32_t)0x00000014UL) |
| |
| #define | MXC_R_CAN_AMR8 ((uint32_t)0x00000014UL) |
| |
| #define | MXC_R_CAN_ECC ((uint32_t)0x00000018UL) |
| |
| #define | MXC_R_CAN_RXERR ((uint32_t)0x00000019UL) |
| |
| #define | MXC_R_CAN_TXERR ((uint32_t)0x0000001AUL) |
| |
| #define | MXC_R_CAN_ALC ((uint32_t)0x0000001BUL) |
| |
| #define | MXC_R_CAN_NBT ((uint32_t)0x0000001CUL) |
| |
| #define | MXC_R_CAN_DBT_SSPP ((uint32_t)0x00000020UL) |
| |
| #define | MXC_R_CAN_FDCTRL ((uint32_t)0x00000024UL) |
| |
| #define | MXC_R_CAN_FDSTAT ((uint32_t)0x00000025UL) |
| |
| #define | MXC_R_CAN_DPERR ((uint32_t)0x00000026UL) |
| |
| #define | MXC_R_CAN_APERR ((uint32_t)0x00000027UL) |
| |
| #define | MXC_R_CAN_TEST ((uint32_t)0x00000028UL) |
| |
| #define | MXC_R_CAN_WUPCLKDIV ((uint32_t)0x00000029UL) |
| |
| #define | MXC_R_CAN_WUPFT ((uint32_t)0x0000002AUL) |
| |
| #define | MXC_R_CAN_WUPET ((uint32_t)0x0000002CUL) |
| |
| #define | MXC_R_CAN_RXDCNT ((uint32_t)0x00000030UL) |
| |
| #define | MXC_R_CAN_TXSCNT ((uint32_t)0x00000032UL) |
| |
| #define | MXC_R_CAN_TXDECMP ((uint32_t)0x00000033UL) |
| |
| #define | MXC_R_CAN_EINTFL ((uint32_t)0x00000034UL) |
| |
| #define | MXC_R_CAN_EINTEN ((uint32_t)0x00000035UL) |
| |
| #define | MXC_R_CAN_RXTO ((uint32_t)0x00000036UL) |
| |
| #define | MXC_F_CAN_MODE_AFM_POS 0 |
| |
| #define | MXC_F_CAN_MODE_AFM ((uint8_t)(0x1UL << MXC_F_CAN_MODE_AFM_POS)) |
| |
| #define | MXC_F_CAN_MODE_LOM_POS 1 |
| |
| #define | MXC_F_CAN_MODE_LOM ((uint8_t)(0x1UL << MXC_F_CAN_MODE_LOM_POS)) |
| |
| #define | MXC_F_CAN_MODE_RST_POS 2 |
| |
| #define | MXC_F_CAN_MODE_RST ((uint8_t)(0x1UL << MXC_F_CAN_MODE_RST_POS)) |
| |
| #define | MXC_F_CAN_MODE_RXTRIG_POS 3 |
| |
| #define | MXC_F_CAN_MODE_RXTRIG ((uint8_t)(0x7UL << MXC_F_CAN_MODE_RXTRIG_POS)) |
| |
| #define | MXC_V_CAN_MODE_RXTRIG_1W ((uint8_t)0x0UL) |
| |
| #define | MXC_S_CAN_MODE_RXTRIG_1W (MXC_V_CAN_MODE_RXTRIG_1W << MXC_F_CAN_MODE_RXTRIG_POS) |
| |
| #define | MXC_V_CAN_MODE_RXTRIG_4W ((uint8_t)0x1UL) |
| |
| #define | MXC_S_CAN_MODE_RXTRIG_4W (MXC_V_CAN_MODE_RXTRIG_4W << MXC_F_CAN_MODE_RXTRIG_POS) |
| |
| #define | MXC_V_CAN_MODE_RXTRIG_8W ((uint8_t)0x2UL) |
| |
| #define | MXC_S_CAN_MODE_RXTRIG_8W (MXC_V_CAN_MODE_RXTRIG_8W << MXC_F_CAN_MODE_RXTRIG_POS) |
| |
| #define | MXC_V_CAN_MODE_RXTRIG_16W ((uint8_t)0x3UL) |
| |
| #define | MXC_S_CAN_MODE_RXTRIG_16W (MXC_V_CAN_MODE_RXTRIG_16W << MXC_F_CAN_MODE_RXTRIG_POS) |
| |
| #define | MXC_V_CAN_MODE_RXTRIG_32W ((uint8_t)0x4UL) |
| |
| #define | MXC_S_CAN_MODE_RXTRIG_32W (MXC_V_CAN_MODE_RXTRIG_32W << MXC_F_CAN_MODE_RXTRIG_POS) |
| |
| #define | MXC_V_CAN_MODE_RXTRIG_64W ((uint8_t)0x5UL) |
| |
| #define | MXC_S_CAN_MODE_RXTRIG_64W (MXC_V_CAN_MODE_RXTRIG_64W << MXC_F_CAN_MODE_RXTRIG_POS) |
| |
| #define | MXC_F_CAN_MODE_DMA_POS 6 |
| |
| #define | MXC_F_CAN_MODE_DMA ((uint8_t)(0x1UL << MXC_F_CAN_MODE_DMA_POS)) |
| |
| #define | MXC_F_CAN_MODE_SLP_POS 7 |
| |
| #define | MXC_F_CAN_MODE_SLP ((uint8_t)(0x1UL << MXC_F_CAN_MODE_SLP_POS)) |
| |
| #define | MXC_F_CAN_CMD_ABORT_POS 1 |
| |
| #define | MXC_F_CAN_CMD_ABORT ((uint8_t)(0x1UL << MXC_F_CAN_CMD_ABORT_POS)) |
| |
| #define | MXC_F_CAN_CMD_TXREQ_POS 2 |
| |
| #define | MXC_F_CAN_CMD_TXREQ ((uint8_t)(0x1UL << MXC_F_CAN_CMD_TXREQ_POS)) |
| |
| #define | MXC_F_CAN_STAT_BUS_OFF_POS 0 |
| |
| #define | MXC_F_CAN_STAT_BUS_OFF ((uint8_t)(0x1UL << MXC_F_CAN_STAT_BUS_OFF_POS)) |
| |
| #define | MXC_F_CAN_STAT_ERR_POS 1 |
| |
| #define | MXC_F_CAN_STAT_ERR ((uint8_t)(0x1UL << MXC_F_CAN_STAT_ERR_POS)) |
| |
| #define | MXC_F_CAN_STAT_TX_POS 2 |
| |
| #define | MXC_F_CAN_STAT_TX ((uint8_t)(0x1UL << MXC_F_CAN_STAT_TX_POS)) |
| |
| #define | MXC_F_CAN_STAT_RX_POS 3 |
| |
| #define | MXC_F_CAN_STAT_RX ((uint8_t)(0x1UL << MXC_F_CAN_STAT_RX_POS)) |
| |
| #define | MXC_F_CAN_STAT_TXBUF_POS 5 |
| |
| #define | MXC_F_CAN_STAT_TXBUF ((uint8_t)(0x1UL << MXC_F_CAN_STAT_TXBUF_POS)) |
| |
| #define | MXC_F_CAN_STAT_DOR_POS 6 |
| |
| #define | MXC_F_CAN_STAT_DOR ((uint8_t)(0x1UL << MXC_F_CAN_STAT_DOR_POS)) |
| |
| #define | MXC_F_CAN_STAT_RXBUF_POS 7 |
| |
| #define | MXC_F_CAN_STAT_RXBUF ((uint8_t)(0x1UL << MXC_F_CAN_STAT_RXBUF_POS)) |
| |
| #define | MXC_F_CAN_INTFL_DOR_POS 0 |
| |
| #define | MXC_F_CAN_INTFL_DOR ((uint8_t)(0x1UL << MXC_F_CAN_INTFL_DOR_POS)) |
| |
| #define | MXC_F_CAN_INTFL_BERR_POS 1 |
| |
| #define | MXC_F_CAN_INTFL_BERR ((uint8_t)(0x1UL << MXC_F_CAN_INTFL_BERR_POS)) |
| |
| #define | MXC_F_CAN_INTFL_TX_POS 2 |
| |
| #define | MXC_F_CAN_INTFL_TX ((uint8_t)(0x1UL << MXC_F_CAN_INTFL_TX_POS)) |
| |
| #define | MXC_F_CAN_INTFL_RX_POS 3 |
| |
| #define | MXC_F_CAN_INTFL_RX ((uint8_t)(0x1UL << MXC_F_CAN_INTFL_RX_POS)) |
| |
| #define | MXC_F_CAN_INTFL_ERPSV_POS 4 |
| |
| #define | MXC_F_CAN_INTFL_ERPSV ((uint8_t)(0x1UL << MXC_F_CAN_INTFL_ERPSV_POS)) |
| |
| #define | MXC_F_CAN_INTFL_ERWARN_POS 5 |
| |
| #define | MXC_F_CAN_INTFL_ERWARN ((uint8_t)(0x1UL << MXC_F_CAN_INTFL_ERWARN_POS)) |
| |
| #define | MXC_F_CAN_INTFL_AL_POS 6 |
| |
| #define | MXC_F_CAN_INTFL_AL ((uint8_t)(0x1UL << MXC_F_CAN_INTFL_AL_POS)) |
| |
| #define | MXC_F_CAN_INTFL_WU_POS 7 |
| |
| #define | MXC_F_CAN_INTFL_WU ((uint8_t)(0x1UL << MXC_F_CAN_INTFL_WU_POS)) |
| |
| #define | MXC_F_CAN_INTEN_DOR_POS 0 |
| |
| #define | MXC_F_CAN_INTEN_DOR ((uint8_t)(0x1UL << MXC_F_CAN_INTEN_DOR_POS)) |
| |
| #define | MXC_F_CAN_INTEN_BERR_POS 1 |
| |
| #define | MXC_F_CAN_INTEN_BERR ((uint8_t)(0x1UL << MXC_F_CAN_INTEN_BERR_POS)) |
| |
| #define | MXC_F_CAN_INTEN_TX_POS 2 |
| |
| #define | MXC_F_CAN_INTEN_TX ((uint8_t)(0x1UL << MXC_F_CAN_INTEN_TX_POS)) |
| |
| #define | MXC_F_CAN_INTEN_RX_POS 3 |
| |
| #define | MXC_F_CAN_INTEN_RX ((uint8_t)(0x1UL << MXC_F_CAN_INTEN_RX_POS)) |
| |
| #define | MXC_F_CAN_INTEN_ERPSV_POS 4 |
| |
| #define | MXC_F_CAN_INTEN_ERPSV ((uint8_t)(0x1UL << MXC_F_CAN_INTEN_ERPSV_POS)) |
| |
| #define | MXC_F_CAN_INTEN_ERWARN_POS 5 |
| |
| #define | MXC_F_CAN_INTEN_ERWARN ((uint8_t)(0x1UL << MXC_F_CAN_INTEN_ERWARN_POS)) |
| |
| #define | MXC_F_CAN_INTEN_AL_POS 6 |
| |
| #define | MXC_F_CAN_INTEN_AL ((uint8_t)(0x1UL << MXC_F_CAN_INTEN_AL_POS)) |
| |
| #define | MXC_F_CAN_INTEN_WU_POS 7 |
| |
| #define | MXC_F_CAN_INTEN_WU ((uint8_t)(0x1UL << MXC_F_CAN_INTEN_WU_POS)) |
| |
| #define | MXC_F_CAN_RMC_NUM_MSGS_POS 0 |
| |
| #define | MXC_F_CAN_RMC_NUM_MSGS ((uint8_t)(0x1FUL << MXC_F_CAN_RMC_NUM_MSGS_POS)) |
| |
| #define | MXC_F_CAN_BUSTIM0_BR_CLKDIV_POS 0 |
| |
| #define | MXC_F_CAN_BUSTIM0_BR_CLKDIV ((uint8_t)(0x3FUL << MXC_F_CAN_BUSTIM0_BR_CLKDIV_POS)) |
| |
| #define | MXC_F_CAN_BUSTIM0_SJW_POS 6 |
| |
| #define | MXC_F_CAN_BUSTIM0_SJW ((uint8_t)(0x3UL << MXC_F_CAN_BUSTIM0_SJW_POS)) |
| |
| #define | MXC_F_CAN_BUSTIM1_TSEG1_POS 0 |
| |
| #define | MXC_F_CAN_BUSTIM1_TSEG1 ((uint8_t)(0xFUL << MXC_F_CAN_BUSTIM1_TSEG1_POS)) |
| |
| #define | MXC_F_CAN_BUSTIM1_TSEG2_POS 4 |
| |
| #define | MXC_F_CAN_BUSTIM1_TSEG2 ((uint8_t)(0x7UL << MXC_F_CAN_BUSTIM1_TSEG2_POS)) |
| |
| #define | MXC_F_CAN_BUSTIM1_SAM_POS 7 |
| |
| #define | MXC_F_CAN_BUSTIM1_SAM ((uint8_t)(0x1UL << MXC_F_CAN_BUSTIM1_SAM_POS)) |
| |
| #define | MXC_F_CAN_TXFIFO32_DATA_POS 0 |
| |
| #define | MXC_F_CAN_TXFIFO32_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_CAN_TXFIFO32_DATA_POS)) |
| |
| #define | MXC_F_CAN_TXFIFO16_DATA_POS 0 |
| |
| #define | MXC_F_CAN_TXFIFO16_DATA ((uint16_t)(0xFFFFUL << MXC_F_CAN_TXFIFO16_DATA_POS)) |
| |
| #define | MXC_F_CAN_TXFIFO8_DATA_POS 0 |
| |
| #define | MXC_F_CAN_TXFIFO8_DATA ((uint8_t)(0xFFUL << MXC_F_CAN_TXFIFO8_DATA_POS)) |
| |
| #define | MXC_F_CAN_RXFIFO32_DATA_POS 0 |
| |
| #define | MXC_F_CAN_RXFIFO32_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_CAN_RXFIFO32_DATA_POS)) |
| |
| #define | MXC_F_CAN_RXFIFO16_DATA_POS 0 |
| |
| #define | MXC_F_CAN_RXFIFO16_DATA ((uint16_t)(0xFFFFUL << MXC_F_CAN_RXFIFO16_DATA_POS)) |
| |
| #define | MXC_F_CAN_RXFIFO8_DATA_POS 0 |
| |
| #define | MXC_F_CAN_RXFIFO8_DATA ((uint8_t)(0xFFUL << MXC_F_CAN_RXFIFO8_DATA_POS)) |
| |
| #define | MXC_F_CAN_ACR32_ACR_POS 0 |
| |
| #define | MXC_F_CAN_ACR32_ACR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CAN_ACR32_ACR_POS)) |
| |
| #define | MXC_F_CAN_ACR16_ACR_POS 0 |
| |
| #define | MXC_F_CAN_ACR16_ACR ((uint16_t)(0xFFFFUL << MXC_F_CAN_ACR16_ACR_POS)) |
| |
| #define | MXC_F_CAN_ACR8_ACR_POS 0 |
| |
| #define | MXC_F_CAN_ACR8_ACR ((uint8_t)(0xFFUL << MXC_F_CAN_ACR8_ACR_POS)) |
| |
| #define | MXC_F_CAN_AMR32_AMR_POS 0 |
| |
| #define | MXC_F_CAN_AMR32_AMR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CAN_AMR32_AMR_POS)) |
| |
| #define | MXC_F_CAN_AMR16_AMR_POS 0 |
| |
| #define | MXC_F_CAN_AMR16_AMR ((uint16_t)(0xFFFFUL << MXC_F_CAN_AMR16_AMR_POS)) |
| |
| #define | MXC_F_CAN_AMR8_AMR_POS 0 |
| |
| #define | MXC_F_CAN_AMR8_AMR ((uint8_t)(0xFFUL << MXC_F_CAN_AMR8_AMR_POS)) |
| |
| #define | MXC_F_CAN_ECC_BER_POS 0 |
| |
| #define | MXC_F_CAN_ECC_BER ((uint8_t)(0x1UL << MXC_F_CAN_ECC_BER_POS)) |
| |
| #define | MXC_F_CAN_ECC_STFER_POS 1 |
| |
| #define | MXC_F_CAN_ECC_STFER ((uint8_t)(0x1UL << MXC_F_CAN_ECC_STFER_POS)) |
| |
| #define | MXC_F_CAN_ECC_CRCER_POS 2 |
| |
| #define | MXC_F_CAN_ECC_CRCER ((uint8_t)(0x1UL << MXC_F_CAN_ECC_CRCER_POS)) |
| |
| #define | MXC_F_CAN_ECC_FRMER_POS 3 |
| |
| #define | MXC_F_CAN_ECC_FRMER ((uint8_t)(0x1UL << MXC_F_CAN_ECC_FRMER_POS)) |
| |
| #define | MXC_F_CAN_ECC_ACKER_POS 4 |
| |
| #define | MXC_F_CAN_ECC_ACKER ((uint8_t)(0x1UL << MXC_F_CAN_ECC_ACKER_POS)) |
| |
| #define | MXC_F_CAN_ECC_EDIR_POS 5 |
| |
| #define | MXC_F_CAN_ECC_EDIR ((uint8_t)(0x1UL << MXC_F_CAN_ECC_EDIR_POS)) |
| |
| #define | MXC_F_CAN_ECC_TXWRN_POS 6 |
| |
| #define | MXC_F_CAN_ECC_TXWRN ((uint8_t)(0x1UL << MXC_F_CAN_ECC_TXWRN_POS)) |
| |
| #define | MXC_F_CAN_ECC_RXWRN_POS 7 |
| |
| #define | MXC_F_CAN_ECC_RXWRN ((uint8_t)(0x1UL << MXC_F_CAN_ECC_RXWRN_POS)) |
| |
| #define | MXC_F_CAN_RXERR_RXERR_POS 0 |
| |
| #define | MXC_F_CAN_RXERR_RXERR ((uint8_t)(0xFFUL << MXC_F_CAN_RXERR_RXERR_POS)) |
| |
| #define | MXC_F_CAN_TXERR_TXERR_POS 0 |
| |
| #define | MXC_F_CAN_TXERR_TXERR ((uint8_t)(0xFFUL << MXC_F_CAN_TXERR_TXERR_POS)) |
| |
| #define | MXC_F_CAN_ALC_ALC_POS 0 |
| |
| #define | MXC_F_CAN_ALC_ALC ((uint8_t)(0x1FUL << MXC_F_CAN_ALC_ALC_POS)) |
| |
| #define | MXC_F_CAN_NBT_NBRP_POS 0 |
| |
| #define | MXC_F_CAN_NBT_NBRP ((uint32_t)(0x3FFUL << MXC_F_CAN_NBT_NBRP_POS)) |
| |
| #define | MXC_F_CAN_NBT_NSEG1_POS 10 |
| |
| #define | MXC_F_CAN_NBT_NSEG1 ((uint32_t)(0xFFUL << MXC_F_CAN_NBT_NSEG1_POS)) |
| |
| #define | MXC_F_CAN_NBT_NSEG2_POS 18 |
| |
| #define | MXC_F_CAN_NBT_NSEG2 ((uint32_t)(0x7FUL << MXC_F_CAN_NBT_NSEG2_POS)) |
| |
| #define | MXC_F_CAN_NBT_NSJW_POS 25 |
| |
| #define | MXC_F_CAN_NBT_NSJW ((uint32_t)(0x7FUL << MXC_F_CAN_NBT_NSJW_POS)) |
| |
| #define | MXC_F_CAN_DBT_SSPP_DBRP_POS 0 |
| |
| #define | MXC_F_CAN_DBT_SSPP_DBRP ((uint32_t)(0x3FFUL << MXC_F_CAN_DBT_SSPP_DBRP_POS)) |
| |
| #define | MXC_F_CAN_DBT_SSPP_DSEG1_POS 10 |
| |
| #define | MXC_F_CAN_DBT_SSPP_DSEG1 ((uint32_t)(0x3FUL << MXC_F_CAN_DBT_SSPP_DSEG1_POS)) |
| |
| #define | MXC_F_CAN_DBT_SSPP_DSEG2_POS 16 |
| |
| #define | MXC_F_CAN_DBT_SSPP_DSEG2 ((uint32_t)(0xFUL << MXC_F_CAN_DBT_SSPP_DSEG2_POS)) |
| |
| #define | MXC_F_CAN_DBT_SSPP_DSJW_POS 20 |
| |
| #define | MXC_F_CAN_DBT_SSPP_DSJW ((uint32_t)(0xFUL << MXC_F_CAN_DBT_SSPP_DSJW_POS)) |
| |
| #define | MXC_F_CAN_DBT_SSPP_SSPP_POS 24 |
| |
| #define | MXC_F_CAN_DBT_SSPP_SSPP ((uint32_t)(0x7FUL << MXC_F_CAN_DBT_SSPP_SSPP_POS)) |
| |
| #define | MXC_F_CAN_FDCTRL_FDEN_POS 0 |
| |
| #define | MXC_F_CAN_FDCTRL_FDEN ((uint8_t)(0x1UL << MXC_F_CAN_FDCTRL_FDEN_POS)) |
| |
| #define | MXC_F_CAN_FDCTRL_BRSEN_POS 1 |
| |
| #define | MXC_F_CAN_FDCTRL_BRSEN ((uint8_t)(0x1UL << MXC_F_CAN_FDCTRL_BRSEN_POS)) |
| |
| #define | MXC_F_CAN_FDCTRL_EXTBT_POS 2 |
| |
| #define | MXC_F_CAN_FDCTRL_EXTBT ((uint8_t)(0x1UL << MXC_F_CAN_FDCTRL_EXTBT_POS)) |
| |
| #define | MXC_F_CAN_FDCTRL_ISO_POS 3 |
| |
| #define | MXC_F_CAN_FDCTRL_ISO ((uint8_t)(0x1UL << MXC_F_CAN_FDCTRL_ISO_POS)) |
| |
| #define | MXC_F_CAN_FDCTRL_DAR_POS 4 |
| |
| #define | MXC_F_CAN_FDCTRL_DAR ((uint8_t)(0x1UL << MXC_F_CAN_FDCTRL_DAR_POS)) |
| |
| #define | MXC_F_CAN_FDCTRL_REOM_POS 5 |
| |
| #define | MXC_F_CAN_FDCTRL_REOM ((uint8_t)(0x1UL << MXC_F_CAN_FDCTRL_REOM_POS)) |
| |
| #define | MXC_F_CAN_FDCTRL_PED_POS 6 |
| |
| #define | MXC_F_CAN_FDCTRL_PED ((uint8_t)(0x1UL << MXC_F_CAN_FDCTRL_PED_POS)) |
| |
| #define | MXC_F_CAN_FDSTAT_BITERR_POS 0 |
| |
| #define | MXC_F_CAN_FDSTAT_BITERR ((uint8_t)(0x1UL << MXC_F_CAN_FDSTAT_BITERR_POS)) |
| |
| #define | MXC_F_CAN_FDSTAT_CRCERR_POS 1 |
| |
| #define | MXC_F_CAN_FDSTAT_CRCERR ((uint8_t)(0x1UL << MXC_F_CAN_FDSTAT_CRCERR_POS)) |
| |
| #define | MXC_F_CAN_FDSTAT_FRMERR_POS 2 |
| |
| #define | MXC_F_CAN_FDSTAT_FRMERR ((uint8_t)(0x1UL << MXC_F_CAN_FDSTAT_FRMERR_POS)) |
| |
| #define | MXC_F_CAN_FDSTAT_STFERR_POS 3 |
| |
| #define | MXC_F_CAN_FDSTAT_STFERR ((uint8_t)(0x1UL << MXC_F_CAN_FDSTAT_STFERR_POS)) |
| |
| #define | MXC_F_CAN_FDSTAT_PEE_POS 4 |
| |
| #define | MXC_F_CAN_FDSTAT_PEE ((uint8_t)(0x1UL << MXC_F_CAN_FDSTAT_PEE_POS)) |
| |
| #define | MXC_F_CAN_FDSTAT_STATE_POS 6 |
| |
| #define | MXC_F_CAN_FDSTAT_STATE ((uint8_t)(0x3UL << MXC_F_CAN_FDSTAT_STATE_POS)) |
| |
| #define | MXC_V_CAN_FDSTAT_STATE_INT ((uint8_t)0x0UL) |
| |
| #define | MXC_S_CAN_FDSTAT_STATE_INT (MXC_V_CAN_FDSTAT_STATE_INT << MXC_F_CAN_FDSTAT_STATE_POS) |
| |
| #define | MXC_V_CAN_FDSTAT_STATE_IDLE ((uint8_t)0x1UL) |
| |
| #define | MXC_S_CAN_FDSTAT_STATE_IDLE (MXC_V_CAN_FDSTAT_STATE_IDLE << MXC_F_CAN_FDSTAT_STATE_POS) |
| |
| #define | MXC_V_CAN_FDSTAT_STATE_RX ((uint8_t)0x2UL) |
| |
| #define | MXC_S_CAN_FDSTAT_STATE_RX (MXC_V_CAN_FDSTAT_STATE_RX << MXC_F_CAN_FDSTAT_STATE_POS) |
| |
| #define | MXC_V_CAN_FDSTAT_STATE_TX ((uint8_t)0x3UL) |
| |
| #define | MXC_S_CAN_FDSTAT_STATE_TX (MXC_V_CAN_FDSTAT_STATE_TX << MXC_F_CAN_FDSTAT_STATE_POS) |
| |
| #define | MXC_F_CAN_DPERR_DPERR_POS 0 |
| |
| #define | MXC_F_CAN_DPERR_DPERR ((uint8_t)(0xFFUL << MXC_F_CAN_DPERR_DPERR_POS)) |
| |
| #define | MXC_F_CAN_APERR_APERR_POS 0 |
| |
| #define | MXC_F_CAN_APERR_APERR ((uint8_t)(0xFFUL << MXC_F_CAN_APERR_APERR_POS)) |
| |
| #define | MXC_F_CAN_TEST_LBEN_POS 0 |
| |
| #define | MXC_F_CAN_TEST_LBEN ((uint8_t)(0x1UL << MXC_F_CAN_TEST_LBEN_POS)) |
| |
| #define | MXC_F_CAN_TEST_TXC_POS 1 |
| |
| #define | MXC_F_CAN_TEST_TXC ((uint8_t)(0x1UL << MXC_F_CAN_TEST_TXC_POS)) |
| |
| #define | MXC_F_CAN_WUPCLKDIV_WUPDIV_POS 0 |
| |
| #define | MXC_F_CAN_WUPCLKDIV_WUPDIV ((uint8_t)(0xFFUL << MXC_F_CAN_WUPCLKDIV_WUPDIV_POS)) |
| |
| #define | MXC_F_CAN_WUPFT_WUPFT_POS 0 |
| |
| #define | MXC_F_CAN_WUPFT_WUPFT ((uint16_t)(0xFFFFUL << MXC_F_CAN_WUPFT_WUPFT_POS)) |
| |
| #define | MXC_F_CAN_WUPET_WUPET_POS 0 |
| |
| #define | MXC_F_CAN_WUPET_WUPET ((uint32_t)(0xFFFFFUL << MXC_F_CAN_WUPET_WUPET_POS)) |
| |
| #define | MXC_F_CAN_RXDCNT_RXDCNT_POS 0 |
| |
| #define | MXC_F_CAN_RXDCNT_RXDCNT ((uint16_t)(0xFFFFUL << MXC_F_CAN_RXDCNT_RXDCNT_POS)) |
| |
| #define | MXC_F_CAN_TXSCNT_TXSCNT_POS 0 |
| |
| #define | MXC_F_CAN_TXSCNT_TXSCNT ((uint8_t)(0xFFUL << MXC_F_CAN_TXSCNT_TXSCNT_POS)) |
| |
| #define | MXC_F_CAN_TXDECMP_TDCO_POS 0 |
| |
| #define | MXC_F_CAN_TXDECMP_TDCO ((uint8_t)(0x7FUL << MXC_F_CAN_TXDECMP_TDCO_POS)) |
| |
| #define | MXC_F_CAN_TXDECMP_TDCEN_POS 7 |
| |
| #define | MXC_F_CAN_TXDECMP_TDCEN ((uint8_t)(0x1UL << MXC_F_CAN_TXDECMP_TDCEN_POS)) |
| |
| #define | MXC_F_CAN_EINTFL_RX_THD_POS 0 |
| |
| #define | MXC_F_CAN_EINTFL_RX_THD ((uint8_t)(0x1UL << MXC_F_CAN_EINTFL_RX_THD_POS)) |
| |
| #define | MXC_F_CAN_EINTFL_RX_TO_POS 1 |
| |
| #define | MXC_F_CAN_EINTFL_RX_TO ((uint8_t)(0x1UL << MXC_F_CAN_EINTFL_RX_TO_POS)) |
| |
| #define | MXC_F_CAN_EINTEN_RX_THD_POS 0 |
| |
| #define | MXC_F_CAN_EINTEN_RX_THD ((uint8_t)(0x1UL << MXC_F_CAN_EINTEN_RX_THD_POS)) |
| |
| #define | MXC_F_CAN_EINTEN_RX_TO_POS 1 |
| |
| #define | MXC_F_CAN_EINTEN_RX_TO ((uint8_t)(0x1UL << MXC_F_CAN_EINTEN_RX_TO_POS)) |
| |
| #define | MXC_F_CAN_RXTO_RX_TO_POS 0 |
| |
| #define | MXC_F_CAN_RXTO_RX_TO ((uint16_t)(0xFFFFUL << MXC_F_CAN_RXTO_RX_TO_POS)) |
| |
1.9.4