Converter Reference

AD9081

AD9081 combined transmit and receive model.

AD9082

AD9081 combined transmit and receive model.

AD9084

AD9084 Receive model.

AD9088

AD9088 Receive model.

AD9680

AD9680 high speed ADC clocking model.

class adijif.converters.ad9680.ad9680(*args: Any, **kwargs: Any)

Bases: ad9680_draw, ad9680_bf

AD9680 high speed ADC model.

This model supports direct clock configurations

Clocking: AD9680 has directly clocked ADC that have optional input dividers. The sample rate can be determined as follows:

baseband_sample_rate = (input_clock / input_clock_divider) / datapath_decimation

get_config(solution: CpoSolveResult | None = None) → Dict

Extract configurations from solver results.

Collect internal converter configuration and output clock definitions leading to connected devices (clock chips, FPGAs)

Args:

solution (CpoSolveResult): CPlex solution. Only needed for CPlex solver

Returns:

Dict: Dictionary of clocking rates and dividers for configuration

get_required_clock_names() → List[str]

Get list of strings of names of requested clocks.

This list of names is for the clocks defined by get_required_clocks

Returns:

List[str]: List of strings of clock names in order

get_required_clocks() → List

Generate list required clocks.

For AD9680 this will contain [converter clock, sysref requirement SOS]

Returns:

List: List of solver variables, equations, and constants

input_clock_max = 4000000000.0

Clocking AD9680 has directly clocked ADCs that have optional input dividers. The sample rate can be determined as follows:

baseband_sample_rate = (input_clock / input_clock_divider) / datapath_decimation

AD9144

AD9144 high speed DAC clocking model.

class adijif.converters.ad9144.ad9144(*args: Any, **kwargs: Any)

Bases: ad9144_bf

AD9144 high speed DAC model.

This model supports both direct clock configurations and on-board generation

Clocking: AD9144 has directly clocked DAC that have optional input dividers. The sample rate can be determined as follows:

baseband_sample_rate = (input_clock / input_clock_divider) / datapath_decimation

get_config(solution: CpoSolveResult | None = None) → Dict

Extract configurations from solver results.

Collect internal converter configuration and output clock definitions leading to connected devices (clock chips, FPGAs)

Args:

solution (CpoSolveResult): CPlex solution. Only needed for CPlex solver

Returns:

Dict: Dictionary of clocking rates and dividers for configuration

get_required_clock_names() → List[str]

Get list of strings of names of requested clocks.

This list of names is for the clocks defined by get_required_clocks

Returns:

List[str]: List of strings of clock names in order

get_required_clocks() → List

Generate list required clocks.

For AD9144 this will contain [converter clock, sysref requirement SOS]

Returns:

List: List of dictionaries of solver components

ADRV9009

ADRV9009 transceiver clocking model.

class adijif.converters.adrv9009.adrv9009(model: None | CpoModel = None, solver: str | None = None)

Bases: adrv9009_core

ADRV9009 combined transmit and receive model.

get_required_clocks() → List[Dict]

Generate list of required clocks.

For ADRV9009 this will contain: [device clock requirement SOS, sysref requirement SOS]

Returns:

list[dict]: List of dictionaries of solver variables, equations, and constants

Raises:

Exception: Invalid relation of rates between RX and TX AssertionError: Gekko called

validate_config() → None

Validate device configurations including JESD and clocks of both ADC and DAC.

This check only is for static configuration that does not include variables which are solved.

class adijif.converters.adrv9009.adrv9009_clock_common(model: None | CpoModel = None, solver: str | None = None)

Bases: adrv9009_core, adrv9009_bf

ADRV9009 class managing common singleton (Rx,Tx) methods.

get_config(solution: CpoSolveResult | None = None) → Dict

Extract configurations from solver results.

Collect internal converter configuration and output clock definitions leading to connected devices (clock chips, FPGAs)

Args:

solution (CpoSolveResult): CPlex solution. Only needed for CPlex solver

Returns:

Dict: Dictionary of clocking rates and dividers for configuration

get_required_clocks() → List[Dict]

Generate list of required clocks.

For ADRV9009 this will contain: [device clock requirement SOS, sysref requirement SOS]

Returns:

list[dict]: List of dictionaries of solver variables, equations, and constants

class adijif.converters.adrv9009.adrv9009_core(model: None | CpoModel = None, solver: str | None = None)

Bases: converter

ADRV9009 transceiver clocking model.

This model manage the JESD configuration and input clock constraints. External LO constraints are not modeled.

Clocking: ADRV9009 uses onboard PLLs to generate the JESD clocks

Lane Rate = I/Q Sample Rate * M * Np * (10 / 8) / L Lane Rate = sample_clock * M * Np * (10 / 8) / L

device_clock_available = None

device_clock_ranges = None

get_config(solution: CpoSolveResult | None = None) → Dict

Extract configurations from solver results.

Collect internal converter configuration and output clock definitions leading to connected devices (clock chips, FPGAs)

Args:

solution (CpoSolveResult): CPlex solution. Only needed for CPlex solver

Returns:

Dict: Dictionary of clocking rates and dividers for configuration

get_required_clock_names() → List[str]

Get list of strings of names of requested clocks.

This list of names is for the clocks defined by get_required_clocks

Returns:

List[str]: List of strings of clock names mapped by get_required_clocks

quick_configuration_modes = None

class adijif.converters.adrv9009.adrv9009_rx(*args: Any, **kwargs: Any)

Bases: adc, adrv9009_clock_common, adrv9009_core

ADRV9009 Receive model.

decimation_available = [4, 5, 8, 10, 16, 20, 32, 40]

ADRV9009 Rx decimation stages.

    +-----------+
    +-----------+ Dec 5 (5) +---------+
    |           +-----------+         |
    |                                 |
    |   +----------+   +----------+   |  +------------+   +--------------+
>---+---+ RHB3 (2) +---+ RHB2 (2) +---+--+ RHB1 (1,2) +---+ RFIR (1,2,4) +
        +----------+   +----------+      +------------+   +--------------+

get_required_clock_names() → List[str]

Get list of strings of names of requested clocks.

This list of names is for the clocks defined by get_required_clocks

Returns:

List[str]: List of strings of clock names mapped by get_required_clocks

class adijif.converters.adrv9009.adrv9009_tx(*args: Any, **kwargs: Any)

Bases: dac, adrv9009_clock_common, adrv9009_core

ADRV9009 Transmit model.

get_required_clock_names() → List[str]

Get list of strings of names of requested clocks.

This list of names is for the clocks defined by get_required_clocks

Returns:

List[str]: List of strings of clock names mapped by get_required_clocks

interpolation_available = [1, 2, 4, 5, 8, 10, 16, 20, 32]

ADRV9009 Tx interpolation stages.

                        +------------+
    +--------------------+ Int 5  (5) +--------------------+
    |                    +------------+                    |
    |                                                      |
    |   +------------+   +------------+   +------------+   |   +--------------+
<---+---+ THB3 (1,2) +---+ THB2 (1,2) +---+ THB1 (1,2) +---+---+ TFIR (1,2,4) +
        +------------+   +------------+   +------------+       +--------------+