PLLs Reference

ADF4030

ADF4030 10-Channel Precision Synchronizer.

class adijif.plls.adf4030.adf4030(model: None | CpoModel = None, solver: str | None = None)

Bases: pll

ADF4030 PLL model.

This model currently supports all divider configurations

https://www.analog.com/media/en/technical-documentation/data-sheets/adf4030.pdf

get_config(solution: CpoSolveResult | None = None) → Dict

Extract configurations from solver results.

Collect internal clock chip configuration and output clock definitions leading to connected devices (converters, FPGAs)

Args:

solution (CpoSolveResult): CPlex solution. Only needed for CPlex solver

Returns:

Dict: Dictionary of clocking rates and dividers for configuration

Raises:

Exception: If solver is not called first

property n: int | List[int]

Feedback divider.

Valid values are 8->255

Returns:

int: Current allowable setting

property o: int | List[int]

Output divider.

Valid values are 10->4095

Returns:

int: Current allowable setting

property r: int | List[int]

Reference divider.

Valid values are 1->31

Returns:

int: Current allowable setting

set_requested_clocks(ref_in: int | float | CpoExpr | None, out_freq: int | List[int], clk_names: List[str]) → None

Define necessary clocks to be generated in model.

Args:

ref_in (int, float, CpoExpr, GK_Intermediate): Reference frequency in hertz out_freq (int): list of required clocks to be output clk_names (List[str]): list of clock names

Raises:

Exception: If out_freq and clk_names are not the same length

ADF4371

ADF4371 Microwave Wideband Synthesizer with Integrated VCO model.

class adijif.plls.adf4371.adf4371(model: None | CpoModel = None, solver: str | None = None)

Bases: pll

ADF4371 PLL model.

This model currently supports all divider configurations

https://www.analog.com/media/en/technical-documentation/data-sheets/adf4371.pdf

property d: int | List[int]

REF-in doubler.

Valid values are 1,2

Returns:

int: Current allowable setting

get_config(solution: CpoSolveResult | None = None) → Dict

Extract configurations from solver results.

Collect internal clock chip configuration and output clock definitions leading to connected devices (converters, FPGAs)

Args:

solution (CpoSolveResult): CPlex solution. Only needed for CPlex solver

Returns:

Dict: Dictionary of clocking rates and dividers for configuration

Raises:

Exception: If solver is not called first

property mode: str | List[str]

Set operational mode.

Options are: fractional, integer or [fractional, integer]

Returns:

str: Current allowable modes

property r: int | List[int]

Reference divider.

Valid values are 0->(2^5-1)

Returns:

int: Current allowable setting

property rf_div: int | List[int]

Output RF divider.

Valid dividers are 1,2,3,4,5,6..32->(even)->4096

Returns:

int: Current allowable dividers

set_requested_clocks(ref_in: int | float | CpoExpr | None, out_freq: int) → None

Define necessary clocks to be generated in model.

Args:

ref_in (int, float, CpoExpr, GK_Intermediate): Reference frequency in hertz out_freq (int): list of required clocks to be output

property t: int | List[int]

Reference divide by 2.

Valid values are 0,1

Returns:

int: Current allowable setting

ADF4382

ADF4382 Microwave Wideband Synthesizer with Integrated VCO model.

class adijif.plls.adf4382.adf4382(model: None | CpoModel = None, solver: str | None = None)

Bases: pll

ADF4382 PLL model.

This model does not support fractional mode

https://www.analog.com/media/en/technical-documentation/data-sheets/adf4382.pdf

property EFM3_MODE: int | List[int]

Set EFM3 optimization mode.

Options are: 0, 4, 5

Returns:

int: Current allowable modes

property d: int | List[int]

REF-in doubler.

Valid values are 1,2

Returns:

int: Current allowable setting

freq_doubler_input_max = 2000000000

PFD frequency ranges

get_config(solution: CpoSolveResult | None = None) → Dict

Extract configurations from solver results.

Collect internal clock chip configuration and output clock definitions leading to connected devices (converters, FPGAs)

Args:

solution (CpoSolveResult): CPlex solution. Only needed for CPlex solver

Returns:

Dict: Dictionary of clocking rates and dividers for configuration

Raises:

Exception: If solver is not called first

input_freq_max = 4500000000

Input reference doubler range

property mode: str | List[str]

Set operational mode.

Options are: fractional, integer or [fractional, integer]

Returns:

str: Current allowable modes

property n: int | List[int]

Feedback divider.

Valid dividers are 1->4096

Returns:

int: Current allowable dividers

property o: int | List[int]

Output RF divider.

Valid dividers are 1,2,4

Returns:

int: Current allowable dividers

property r: int | List[int]

Reference divider.

Valid values are 1->(2^6-1)

Returns:

int: Current allowable setting

property require_phase_sync: bool

Determine if phase sync is required.

Returns:

bool: True if phase sync is required

set_requested_clocks(ref_in: int | float | CpoExpr | None, out_freq: int) → None

Define necessary clocks to be generated in model.

Args:

ref_in (int, float, CpoExpr, GK_Intermediate): Reference frequency in hertz out_freq (int): list of required clocks to be output

adijif.plls.adf4382.to_int(value: int | float | List[int] | List[float]) → int | List[int]

Convert value to int or list of ints.