Reference APIs
- Converter Reference
- Clock Chip Reference
- PLLs Reference
- FPGA Reference
- AMD (Xilinx)
xilinxxilinx.determine_pll()xilinx.device_clock_and_ref_clock_relationxilinx.device_clock_sourcexilinx.force_cpllxilinx.force_qpllxilinx.force_qpll1xilinx.force_separate_device_clockxilinx.force_single_quad_tilexilinx.fpga_generation()xilinx.get_config()xilinx.get_required_clock_names()xilinx.get_required_clocks()xilinx.minimize_fpga_ref_clockxilinx.out_clk_selectxilinx.ref_clock_constraintxilinx.setup_by_dev_kit_name()xilinx.target_Fmaxxilinx.trx_gen()xilinx.trx_variant()
- AMD (Xilinx) Transceivers
- AMD (Xilinx)
- JESD204 Reference
jesdjesd.CFjesd.CSjesd.Djesd.Fjesd.F_availablejesd.HDjesd.Kjesd.K_availablejesd.Ljesd.L_availablejesd.Mjesd.M_availablejesd.Njesd.N_availablejesd.Npjesd.Np_availablejesd.Sjesd.available_jesd_modesjesd.bit_clockjesd.bit_clock_maxjesd.bit_clock_minjesd.data_path_widthjesd.device_clockjesd.encodingjesd.encoding_djesd.encoding_njesd.frame_clockjesd.get_jesd_config()jesd.jesd_classjesd.multiframe_clockjesd.sample_clockjesd.validate_clocks()