Reference APIs

• Converter Reference
  • AD9081
    • AD9081 RX diagram
    • AD9081 TX diagram
  • AD9082
    • AD9082 RX diagram
  • AD9084
    • AD9084 RX diagram
  • AD9088
    • AD9088 RX diagram
  • AD9680
    • AD9680 diagram
      • ad9680
        • ad9680.get_config()
        • ad9680.get_required_clock_names()
        • ad9680.get_required_clocks()
        • ad9680.input_clock_max
  • AD9144
    • AD9144 diagram
      • ad9144
        • ad9144.get_config()
        • ad9144.get_required_clock_names()
        • ad9144.get_required_clocks()
  • AD9152
    • AD9152 diagram
      • ad9152
        • ad9152.datapath
        • ad9152.get_required_clock_names()
        • ad9152.interpolation
  • ADRV9009
    • ADRV9009 RX diagram
    • ADRV9009 TX diagram
      • adrv9009
        • adrv9009.get_required_clocks()
        • adrv9009.validate_config()
      • adrv9009_clock_common
        • adrv9009_clock_common.get_config()
        • adrv9009_clock_common.get_required_clocks()
      • adrv9009_core
        • adrv9009_core.device_clock_available
        • adrv9009_core.device_clock_ranges
        • adrv9009_core.get_config()
        • adrv9009_core.get_required_clock_names()
        • adrv9009_core.quick_configuration_modes
      • adrv9009_rx
        • adrv9009_rx.decimation_available
        • adrv9009_rx.get_required_clock_names()
      • adrv9009_tx
        • adrv9009_tx.get_required_clock_names()
        • adrv9009_tx.interpolation_available
• Clock Chip Reference
  • AD9523
    • AD9523-1 diagram
      • ad9523_1
        • ad9523_1.d
        • ad9523_1.get_config()
        • ad9523_1.m1
        • ad9523_1.n2
        • ad9523_1.r2
        • ad9523_1.request_clock_constraint()
        • ad9523_1.set_requested_clocks()
        • ad9523_1.setup_constraints()
  • AD9528
    • AD9528 diagram
      • ad9528
        • ad9528.a
        • ad9528.b
        • ad9528.b_availble
        • ad9528.d
        • ad9528.d_available
        • ad9528.get_config()
        • ad9528.k
        • ad9528.k_available
        • ad9528.m1
        • ad9528.m1_available
        • ad9528.n2
        • ad9528.n2_available
        • ad9528.name
        • ad9528.r1
        • ad9528.request_clock_constraint()
        • ad9528.set_requested_clocks()
        • ad9528.setup_constraints()
        • ad9528.sysref
        • ad9528.vco
  • AD9545
    • AD9545 diagram
      • ad9545
        • ad9545.APLL_PFD_MAX
        • ad9545.PLL_used
        • ad9545.Q_min
        • ad9545.R_min
        • ad9545.draw()
        • ad9545.find_dividers()
        • ad9545.get_config()
        • ad9545.list_available_references()
        • ad9545.set_requested_clocks()
        • ad9545.setup_constraints()
  • HMC7044
    • HMC7044 diagram
      • hmc7044
        • hmc7044.d
        • hmc7044.draw()
        • hmc7044.get_config()
        • hmc7044.n2
        • hmc7044.r2
        • hmc7044.r2_available
        • hmc7044.request_clock_constraint()
        • hmc7044.set_requested_clocks()
        • hmc7044.setup_constraints()
        • hmc7044.vcxo_doubler
  • LTC6952
    • LTC6952 diagram
      • ltc6952
        • ltc6952.d
        • ltc6952.get_config()
        • ltc6952.n2
        • ltc6952.n2_available
        • ltc6952.r2
        • ltc6952.request_clock_constraint()
        • ltc6952.set_requested_clocks()
        • ltc6952.setup_constraints()
        • ltc6952.vco_max
        • ltc6952.vco_min
  • LTC6953
    • LTC6953 diagram
      • ltc6953
        • ltc6953.draw()
        • ltc6953.find_dividers()
        • ltc6953.get_config()
        • ltc6953.list_available_references()
        • ltc6953.m
        • ltc6953.m_available
        • ltc6953.request_clock_constraint()
        • ltc6953.set_requested_clocks()
        • ltc6953.setup_constraints()
• PLLs Reference
  • ADF4030
    • adf4030
      • adf4030.get_config()
      • adf4030.n
      • adf4030.o
      • adf4030.r
      • adf4030.request_clock_constraint()
      • adf4030.set_requested_clocks()
      • adf4030.setup_constraints()
    • adf4030_drawer
      • adf4030_drawer.draw()
  • ADF4371
    • adf4371
      • adf4371.d
      • adf4371.get_config()
      • adf4371.mode
      • adf4371.r
      • adf4371.request_clock_constraint()
      • adf4371.rf_div
      • adf4371.set_requested_clocks()
      • adf4371.setup_constraints()
      • adf4371.t
    • adf4371_drawer
      • adf4371_drawer.draw()
  • ADF4382
    • adf4382
      • adf4382.EFM3_MODE
      • adf4382.d
      • adf4382.freq_doubler_input_max
      • adf4382.get_config()
      • adf4382.input_freq_max
      • adf4382.mode
      • adf4382.n
      • adf4382.o
      • adf4382.r
      • adf4382.request_clock_constraint()
      • adf4382.require_phase_sync
      • adf4382.set_requested_clocks()
      • adf4382.setup_constraints()
    • adf4382_drawer
      • adf4382_drawer.draw()
    • to_int()
• FPGA Reference
  • AMD (Xilinx)
    • Xilinx FPGA diagram
      • xilinx
        • xilinx.determine_pll()
        • xilinx.device_clock_and_ref_clock_relation
        • xilinx.device_clock_source
        • xilinx.force_cpll
        • xilinx.force_qpll
        • xilinx.force_qpll1
        • xilinx.force_separate_device_clock
        • xilinx.force_single_quad_tile
        • xilinx.fpga_generation()
        • xilinx.get_config()
        • xilinx.get_required_clock_names()
        • xilinx.get_required_clocks()
        • xilinx.name
        • xilinx.out_clk_select
        • xilinx.ref_clock_constraint
        • xilinx.setup_by_dev_kit_name()
        • xilinx.target_Fmax
        • xilinx.trx_gen()
        • xilinx.trx_variant()
    • AMD (Xilinx) Transceivers
      • AMD (Xilinx) 7 Series Transceivers
        • CPLL
          • CPLL.D
          • CPLL.M
          • CPLL.N1
          • CPLL.N2
          • CPLL.add_constraints()
          • CPLL.get_config()
          • CPLL.vco_max
          • CPLL.vco_min
        • QPLL
          • QPLL.D
          • QPLL.M
          • QPLL.N
          • QPLL.add_constraints()
          • QPLL.get_config()
          • QPLL.vco_max
          • QPLL.vco_min
        • SevenSeries
          • SevenSeries.add_constraints()
          • SevenSeries.add_plls()
          • SevenSeries.get_config()
      • AMD (Xilinx) UltraScale+ Transceivers
        • CPLL
          • CPLL.vco_max
          • CPLL.vco_min
        • QPLL
          • QPLL.QPLL_CLKOUTRATE
          • QPLL.QPLL_CLKOUTRATE_available
          • QPLL.SDMDATA_max
          • QPLL.SDMDATA_min
          • QPLL.SDMWIDTH
          • QPLL.add_constraints()
          • QPLL.get_config()
          • QPLL.vco_max
          • QPLL.vco_min
        • QPLL1
          • QPLL1.vco_max
          • QPLL1.vco_min
        • UltraScalePlus
          • UltraScalePlus.add_constraints()
          • UltraScalePlus.add_plls()
          • UltraScalePlus.get_config()
• JESD204 Reference
  • jesd
    • jesd.CF
    • jesd.CS
    • jesd.D
    • jesd.F
    • jesd.F_available
    • jesd.HD
    • jesd.K
    • jesd.K_available
    • jesd.L
    • jesd.L_available
    • jesd.M
    • jesd.M_available
    • jesd.N
    • jesd.N_available
    • jesd.Np
    • jesd.Np_available
    • jesd.S
    • jesd.available_jesd_modes
    • jesd.bit_clock
    • jesd.bit_clock_max
    • jesd.bit_clock_min
    • jesd.data_path_width
    • jesd.device_clock
    • jesd.encoding
    • jesd.encoding_d
    • jesd.encoding_n
    • jesd.frame_clock
    • jesd.get_jesd_config()
    • jesd.jesd_class
    • jesd.multiframe_clock
    • jesd.sample_clock
    • jesd.validate_clocks()
• Architecture Tools Reference
  • adijif.plls.utils.adf4030_arch
    • Adf4030Architecture
      • Adf4030Architecture._build_unit_board_node()
      • Adf4030Architecture.draw()
      • Adf4030Architecture.partition
      • Adf4030Architecture.summary
    • Aion_per_FPGA_cascade()
    • Aion_per_FPGA_tree()
    • Apollo_per_Aion_cascade()
    • Apollo_per_Aion_tree()
    • _connect_aions_cascade()
    • _connect_aions_hybrid()
    • _connect_aions_hybrid2()
    • _connect_aions_tree()
    • _split_branches()
    • convert_sec_into_hms()