FPGA Reference
AMD (Xilinx)
Xilinx FPGA clocking model.
- class adijif.fpgas.xilinx.xilinx(model: None | CpoModel = None, solver: str | None = None)
Bases:
xilinx_bf,xilinx_drawXilinx FPGA clocking model.
This model captures different limitations of the Xilinx PLLs and interfaces used for JESD.
Currently only Zynq 7000 devices have been fully tested.
- determine_pll(bit_clock: int, fpga_ref_clock: int) Dict
Determine if configuration is possible with CPLL or QPLL.
CPLL is checked first and will check QPLL if that case is invalid.
This is only used for brute-force implementations.
- Args:
bit_clock (int): Equivalent to lane rate in bits/second fpga_ref_clock (int): System reference clock
- Returns:
Dict: Dictionary of PLL configuration
- property device_clock_and_ref_clock_relation: str
Get device clock and reference clock relation.
Device clock and reference clock relation can be set to: - NA: No relation - ref_clock_2x_device_clock: Reference clock is 2x device clock - ref_clock_eq_device_clock: Reference clock is equal to device clock
- Returns:
str: Device clock and reference clock relation.
- property device_clock_source: str
Get device clock source.
Device clock source can be set to: - external: External clock from clock chip - link_clock: Link layer clock is reused for as device clock - ref_clock: Reference clock is reused for device clock
- Returns:
str: Device clock source.
- force_cpll = False
Force all transceiver sources to be from a single PLL quad. This will try to leverage the output dividers of the PLLs
- force_separate_device_clock: bool = False
Constrain reference clock to be specific values. Options: - CORE_CLOCK: Make reference clock the same as the core clock (LR/40 or LR/66) - CORE_CLOCK_DIV2: Make reference clock the same as the core clock divided by 2 - Unconstrained: No constraints on reference clock. Simply meet PLL constraints
- force_single_quad_tile = False
Request that clock chip generated device clock device clock == LMFC/40 NOTE: THIS IS NOT FPGA REF CLOCK
- fpga_generation() str
Get FPGA generation 7000, US, US+… based on transceiver type.
- Returns:
str: FPGA generation
- Raises:
Exception: Unknown transceiver generation
- get_config(converter: converter, fpga_ref: float | int, solution: CpoSolveResult | None = None) List[Dict] | Dict
Extract configurations from solver results.
Collect internal FPGA configuration and output clock definitions.
- Args:
- converter (conv): Converter object connected to FPGA who config is
collected
- fpga_ref (int or float): Reference clock generated for FPGA for specific
converter
- solution (CpoSolveResult): CPlex solution and only needed for CPlex
solver
- Returns:
Dict: Dictionary of clocking rates and dividers for configuration.
- Raises:
Exception: Invalid PLL configuration.
- get_required_clock_names() List[str]
Get list of strings of names of requested clocks.
This list of names is for the clocks defined by get_required_clocks
- Returns:
List[str]: List of strings of clock names in order
- Raises:
- Exception: Clock have not been enumerated aka get_required_clocks not
not called yet.
- get_required_clocks(converter: converter, fpga_ref: int | None | CpoIntVar, link_out_ref: int | None | CpoIntVar = None) List
Get necessary clocks for QPLL/CPLL configuration.
- Args:
- converter (conv): Converter object of converter connected to
FPGA
- fpga_ref (int, GKVariable, GK_Intermediate, GK_Operators, CpoIntVar):
Abstract or concrete reference to FPGA reference clock
- link_out_ref (int or GKVariable): Reference clock generated for FPGA
link layer output, also called device clock
- Returns:
List: List of solver variables and constraints
- Raises:
Exception: If solver is not valid Exception: Link layer out clock required
- minimize_fpga_ref_clock = False
Force generation of separate device clock from the clock chip. In many cases, the ref clock and device clock can be the same.
- property out_clk_select: int | float
Get current PLL clock output mux options for link layer clock.
Valid options are: “XCVR_REFCLK”, “XCVR_REFCLK_DIV2”, “XCVR_PROGDIV_CLK” If a list of these is provided, the solver will determine one to use.
- Returns:
str, list(str): Mux selection for link layer clock.
- property ref_clock_constraint: str
Get reference clock constraint.
Reference clock constraint can be set to: - CORE_CLOCK: Make reference clock the same as the core clock (LR/40 or LR/66) - CORE_CLOCK_DIV2: Make reference clock the same as the core clock divided by 2 - Unconstrained: No constraints on reference clock. Simply meet PLL constraints
- Returns:
str: Reference clock constraint.
AMD (Xilinx) Transceivers
AMD (Xilinx) 7 Series Transceivers
7 series transceiver model.
- class adijif.fpgas.xilinx.sevenseries.CPLL(parent_transceiver: CpoModel)
Bases:
PLLCommonChannel PLL (CPLL) for 7 series FPGAs.
- add_constraints(config: dict, fpga_ref: int | CpoIntVar, converter: converter) dict
Add Channel PLL (CPLL) constraints.
- Args:
config (dict): Configuration dictionary. fpga_ref (int, CpoIntVar): FPGA reference clock. converter (conv): Converter object.
- Returns:
dict: Updated configuration dictionary.
- get_config(config: dict, converter: converter, fpga_ref: int | CpoIntVar) dict
Get CPLL configuration.
- Args:
config (dict): Configuration dictionary. converter (conv): Converter object. fpga_ref (int, CpoIntVar): FPGA reference clock.
- Returns:
dict: Updated configuration dictionary.
- class adijif.fpgas.xilinx.sevenseries.QPLL(parent_transceiver: CpoModel)
Bases:
PLLCommonQPLL for 7 series FPGAs.
- add_constraints(config: dict, fpga_ref: int | CpoIntVar, converter: converter) dict
Add constraints for QPLL for 7 series FPGAs.
- Args:
config (dict): Configuration dictionary. fpga_ref (int, CpoIntVar): FPGA reference clock. converter (conv): Converter object.
- Returns:
dict: Updated configuration dictionary.
- Raises:
Exception: Unsupported transceiver type.
- get_config(config: dict, converter: converter, fpga_ref: int | float) dict
Get QPLL configuration for 7 series FPGAs.
- Args:
config (dict): Configuration dictionary. converter (conv): Converter object. fpga_ref (Union[int, float]): FPGA reference clock.
- Returns:
dict: Updated configuration dictionary.
- class adijif.fpgas.xilinx.sevenseries.SevenSeries(parent=None, speed_grade: str | None = '-2', transceiver_type: str | None = 'GTXE2', *args, **kwargs)
Bases:
XilinxPLL7 series Transceiver model.
AMD (Xilinx) UltraScale+ Transceivers
Ultrascale+ PLLs transceiver models.
- class adijif.fpgas.xilinx.ultrascaleplus.CPLL(parent_transceiver: CpoModel)
Bases:
CPLLCPLL model for Ultrascale+ transceivers.
- class adijif.fpgas.xilinx.ultrascaleplus.QPLL(parent_transceiver: CpoModel)
Bases:
QPLLQPLL model for Ultrascale+ transceivers.
- add_constraints(config: dict, fpga_ref: int | None | CpoIntVar, converter: converter) dict
Add constraints for the Transceiver.
- Args:
config (dict): Configuration dictionary. fpga_ref (int, CpoIntVar): FPGA reference clock. converter (conv): Converter object.
- Returns:
dict: Updated configuration dictionary.
- class adijif.fpgas.xilinx.ultrascaleplus.QPLL1(parent_transceiver: CpoModel)
Bases:
QPLLQPLL1 model for Ultrascale+ transceivers.
- class adijif.fpgas.xilinx.ultrascaleplus.UltraScalePlus(parent=None, speed_grade: str | None = '-2', transceiver_type: str | None = 'GTXE2', *args, **kwargs)
Bases:
XilinxPLL,core,gekko_translationUltrascale+ PLLs transceiver models.