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ad9434 Reference Design Integration

This page outlines the HDL reference design integration for the ad9434 reference design for the Analog Devices AD9434 component. The IP-Core Generation follow is available on the based on the following base HDL reference design for the following board and design variants:

Reference Design

HDL Reference Design with Custom IP from HDL-Coder. Click on sub-blocks for more documentation.

The IP-Core generation flow will integrate IP generated from Simulink subsystem into an ADI authored reference design. Depending on the FPGA carrier and FMC card or SoM, this will support different IP locations based on the diagram above.

HDL Worflow Advisor Port Mappings

When using the HDL Worflow Advisor, the following port mappings are used to connect the reference design to the HDL-Coder generated IP-Core:

Type Target Platform Interface (MATLAB) Reference Design Connection (Vivado) Width Reference Design Variant
VALID-IN IP Valid Rx Data IN axi_ad9434/adc_valid 1 RX
VALID-OUT IP Data Valid OUT axi_ad9434_dma/fifo_wr_en 1 RX
DATA-IN AD9434 ADC Data 0 IN xlslice_0/Dout 12 RX
DATA-IN AD9434 ADC Data 1 IN xlslice_1/Dout 12 RX
DATA-IN AD9434 ADC Data 2 IN xlslice_2/Dout 12 RX
DATA-IN AD9434 ADC Data 3 IN xlslice_3/Dout 12 RX
DATA-OUT IP Data 0 OUT xlconcat_0/In0 12 RX
DATA-OUT IP Data 1 OUT xlconcat_0/In1 12 RX
DATA-OUT IP Data 2 OUT xlconcat_0/In2 12 RX
DATA-OUT IP Data 3 OUT xlconcat_0/In3 12 RX