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fmcjesdadc1 Reference Design Integration

This page outlines the HDL reference design integration for the fmcjesdadc1 reference design for the Analog Devices FMCJESDADC1 component. The IP-Core Generation follow is available on the based on the following base HDL reference design for the following board and design variants:

Reference Design

HDL Reference Design with Custom IP from HDL-Coder. Click on sub-blocks for more documentation.

The IP-Core generation flow will integrate IP generated from Simulink subsystem into an ADI authored reference design. Depending on the FPGA carrier and FMC card or SoM, this will support different IP locations based on the diagram above.

HDL Worflow Advisor Port Mappings

When using the HDL Worflow Advisor, the following port mappings are used to connect the reference design to the HDL-Coder generated IP-Core:

Type Target Platform Interface (MATLAB) Reference Design Connection (Vivado) Width Reference Design Variant
VALID-OUT IP Data Valid OUT axi_ad9250_cpack/fifo_wr_en 1 RX
VALID-IN IP Valid Rx Data IN axi_ad9250_core/adc_valid_0 1 RX
DATA-OUT IP Data 0 OUT axi_ad9250_cpack/fifo_wr_data_0 32 RX
DATA-OUT IP Data 1 OUT axi_ad9250_cpack/fifo_wr_data_1 32 RX
DATA-OUT IP Data 2 OUT axi_ad9250_cpack/fifo_wr_data_2 32 RX
DATA-OUT IP Data 3 OUT axi_ad9250_cpack/fifo_wr_data_3 32 RX
DATA-IN FMCJESDADC1 ADC Data 0 IN axi_ad9250_core/adc_data_0 32 RX
DATA-IN FMCJESDADC1 ADC Data 1 IN axi_ad9250_core/adc_data_1 32 RX
DATA-IN FMCJESDADC1 ADC Data 2 IN axi_ad9250_core/adc_data_2 32 RX
DATA-IN FMCJESDADC1 ADC Data 3 IN axi_ad9250_core/adc_data_3 32 RX