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#define | MXC_R_I2C_CTRL ((uint32_t)0x00000000UL) |
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#define | MXC_R_I2C_STATUS ((uint32_t)0x00000004UL) |
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#define | MXC_R_I2C_INT_FL0 ((uint32_t)0x00000008UL) |
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#define | MXC_R_I2C_INT_EN0 ((uint32_t)0x0000000CUL) |
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#define | MXC_R_I2C_INT_FL1 ((uint32_t)0x00000010UL) |
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#define | MXC_R_I2C_INT_EN1 ((uint32_t)0x00000014UL) |
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#define | MXC_R_I2C_FIFO_LEN ((uint32_t)0x00000018UL) |
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#define | MXC_R_I2C_RX_CTRL0 ((uint32_t)0x0000001CUL) |
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#define | MXC_R_I2C_RX_CTRL1 ((uint32_t)0x00000020UL) |
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#define | MXC_R_I2C_TX_CTRL0 ((uint32_t)0x00000024UL) |
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#define | MXC_R_I2C_TX_CTRL1 ((uint32_t)0x00000028UL) |
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#define | MXC_R_I2C_FIFO ((uint32_t)0x0000002CUL) |
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#define | MXC_R_I2C_MASTER_CTRL ((uint32_t)0x00000030UL) |
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#define | MXC_R_I2C_CLK_LO ((uint32_t)0x00000034UL) |
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#define | MXC_R_I2C_CLK_HI ((uint32_t)0x00000038UL) |
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#define | MXC_R_I2C_HS_CLK ((uint32_t)0x0000003CUL) |
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#define | MXC_R_I2C_TIMEOUT ((uint32_t)0x00000040UL) |
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#define | MXC_R_I2C_DMA ((uint32_t)0x00000048UL) |
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#define | MXC_R_I2C_SLAVE_ADDR ((uint32_t)0x0000004CUL) |
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#define | MXC_F_I2C_CTRL_I2C_EN_POS 0 |
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#define | MXC_F_I2C_CTRL_I2C_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_I2C_EN_POS)) |
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#define | MXC_F_I2C_CTRL_MST_POS 1 |
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#define | MXC_F_I2C_CTRL_MST ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_MST_POS)) |
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#define | MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS 2 |
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#define | MXC_F_I2C_CTRL_GEN_CALL_ADDR ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS)) |
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#define | MXC_F_I2C_CTRL_RX_MODE_POS 3 |
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#define | MXC_F_I2C_CTRL_RX_MODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_RX_MODE_POS)) |
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#define | MXC_F_I2C_CTRL_RX_MODE_ACK_POS 4 |
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#define | MXC_F_I2C_CTRL_RX_MODE_ACK ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_RX_MODE_ACK_POS)) |
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#define | MXC_F_I2C_CTRL_SCL_OUT_POS 6 |
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#define | MXC_F_I2C_CTRL_SCL_OUT ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_OUT_POS)) |
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#define | MXC_F_I2C_CTRL_SDA_OUT_POS 7 |
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#define | MXC_F_I2C_CTRL_SDA_OUT ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SDA_OUT_POS)) |
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#define | MXC_F_I2C_CTRL_SCL_POS 8 |
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#define | MXC_F_I2C_CTRL_SCL ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_POS)) |
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#define | MXC_F_I2C_CTRL_SDA_POS 9 |
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#define | MXC_F_I2C_CTRL_SDA ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SDA_POS)) |
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#define | MXC_F_I2C_CTRL_SW_OUT_EN_POS 10 |
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#define | MXC_F_I2C_CTRL_SW_OUT_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SW_OUT_EN_POS)) |
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#define | MXC_F_I2C_CTRL_READ_POS 11 |
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#define | MXC_F_I2C_CTRL_READ ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_READ_POS)) |
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#define | MXC_F_I2C_CTRL_SCL_CLK_STRETCH_DIS_POS 12 |
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#define | MXC_F_I2C_CTRL_SCL_CLK_STRETCH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_CLK_STRETCH_DIS_POS)) |
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#define | MXC_F_I2C_CTRL_SCL_PP_MODE_POS 13 |
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#define | MXC_F_I2C_CTRL_SCL_PP_MODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_PP_MODE_POS)) |
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#define | MXC_F_I2C_CTRL_HS_MODE_POS 15 |
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#define | MXC_F_I2C_CTRL_HS_MODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_HS_MODE_POS)) |
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#define | MXC_F_I2C_STATUS_BUS_POS 0 |
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#define | MXC_F_I2C_STATUS_BUS ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_BUS_POS)) |
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#define | MXC_F_I2C_STATUS_RX_EMPTY_POS 1 |
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#define | MXC_F_I2C_STATUS_RX_EMPTY ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RX_EMPTY_POS)) |
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#define | MXC_F_I2C_STATUS_RX_FULL_POS 2 |
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#define | MXC_F_I2C_STATUS_RX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RX_FULL_POS)) |
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#define | MXC_F_I2C_STATUS_TX_EMPTY_POS 3 |
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#define | MXC_F_I2C_STATUS_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TX_EMPTY_POS)) |
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#define | MXC_F_I2C_STATUS_TX_FULL_POS 4 |
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#define | MXC_F_I2C_STATUS_TX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TX_FULL_POS)) |
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#define | MXC_F_I2C_STATUS_CLK_MODE_POS 5 |
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#define | MXC_F_I2C_STATUS_CLK_MODE ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_CLK_MODE_POS)) |
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#define | MXC_F_I2C_INT_FL0_DONE_POS 0 |
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#define | MXC_F_I2C_INT_FL0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_DONE_POS)) |
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#define | MXC_F_I2C_INT_FL0_RX_MODE_POS 1 |
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#define | MXC_F_I2C_INT_FL0_RX_MODE ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_RX_MODE_POS)) |
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#define | MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS 2 |
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#define | MXC_F_I2C_INT_FL0_GEN_CALL_ADDR ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS)) |
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#define | MXC_F_I2C_INT_FL0_ADDR_MATCH_POS 3 |
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#define | MXC_F_I2C_INT_FL0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_ADDR_MATCH_POS)) |
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#define | MXC_F_I2C_INT_FL0_RX_THRESH_POS 4 |
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#define | MXC_F_I2C_INT_FL0_RX_THRESH ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_RX_THRESH_POS)) |
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#define | MXC_F_I2C_INT_FL0_TX_THRESH_POS 5 |
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#define | MXC_F_I2C_INT_FL0_TX_THRESH ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_TX_THRESH_POS)) |
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#define | MXC_F_I2C_INT_FL0_STOP_POS 6 |
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#define | MXC_F_I2C_INT_FL0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_STOP_POS)) |
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#define | MXC_F_I2C_INT_FL0_ADDR_ACK_POS 7 |
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#define | MXC_F_I2C_INT_FL0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_ADDR_ACK_POS)) |
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#define | MXC_F_I2C_INT_FL0_ARB_ER_POS 8 |
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#define | MXC_F_I2C_INT_FL0_ARB_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_ARB_ER_POS)) |
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#define | MXC_F_I2C_INT_FL0_TO_ER_POS 9 |
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#define | MXC_F_I2C_INT_FL0_TO_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_TO_ER_POS)) |
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#define | MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS 10 |
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#define | MXC_F_I2C_INT_FL0_ADDR_NACK_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS)) |
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#define | MXC_F_I2C_INT_FL0_DATA_ER_POS 11 |
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#define | MXC_F_I2C_INT_FL0_DATA_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_DATA_ER_POS)) |
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#define | MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS 12 |
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#define | MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS)) |
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#define | MXC_F_I2C_INT_FL0_START_ER_POS 13 |
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#define | MXC_F_I2C_INT_FL0_START_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_START_ER_POS)) |
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#define | MXC_F_I2C_INT_FL0_STOP_ER_POS 14 |
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#define | MXC_F_I2C_INT_FL0_STOP_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_STOP_ER_POS)) |
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#define | MXC_F_I2C_INT_FL0_TX_LOCK_OUT_POS 15 |
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#define | MXC_F_I2C_INT_FL0_TX_LOCK_OUT ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_TX_LOCK_OUT_POS)) |
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#define | MXC_F_I2C_INT_FL0_RD_ADDR_MATCH_POS 22 |
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#define | MXC_F_I2C_INT_FL0_RD_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_RD_ADDR_MATCH_POS)) |
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#define | MXC_F_I2C_INT_FL0_WR_ADDR_MATCH_POS 23 |
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#define | MXC_F_I2C_INT_FL0_WR_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_WR_ADDR_MATCH_POS)) |
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#define | MXC_F_I2C_INT_EN0_DONE_POS 0 |
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#define | MXC_F_I2C_INT_EN0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_DONE_POS)) |
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#define | MXC_F_I2C_INT_EN0_RX_MODE_POS 1 |
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#define | MXC_F_I2C_INT_EN0_RX_MODE ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_RX_MODE_POS)) |
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#define | MXC_F_I2C_INT_EN0_GEN_CALL_ADDR_POS 2 |
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#define | MXC_F_I2C_INT_EN0_GEN_CALL_ADDR ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_GEN_CALL_ADDR_POS)) |
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#define | MXC_F_I2C_INT_EN0_ADDR_MATCH_POS 3 |
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#define | MXC_F_I2C_INT_EN0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_ADDR_MATCH_POS)) |
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#define | MXC_F_I2C_INT_EN0_RX_THRESH_POS 4 |
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#define | MXC_F_I2C_INT_EN0_RX_THRESH ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_RX_THRESH_POS)) |
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#define | MXC_F_I2C_INT_EN0_TX_THRESH_POS 5 |
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#define | MXC_F_I2C_INT_EN0_TX_THRESH ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_TX_THRESH_POS)) |
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#define | MXC_F_I2C_INT_EN0_STOP_POS 6 |
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#define | MXC_F_I2C_INT_EN0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_STOP_POS)) |
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#define | MXC_F_I2C_INT_EN0_ADDR_ACK_POS 7 |
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#define | MXC_F_I2C_INT_EN0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_ADDR_ACK_POS)) |
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#define | MXC_F_I2C_INT_EN0_ARB_ER_POS 8 |
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#define | MXC_F_I2C_INT_EN0_ARB_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_ARB_ER_POS)) |
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#define | MXC_F_I2C_INT_EN0_TO_ER_POS 9 |
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#define | MXC_F_I2C_INT_EN0_TO_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_TO_ER_POS)) |
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#define | MXC_F_I2C_INT_EN0_ADDR_NACK_ER_POS 10 |
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#define | MXC_F_I2C_INT_EN0_ADDR_NACK_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_ADDR_NACK_ER_POS)) |
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#define | MXC_F_I2C_INT_EN0_DATA_ER_POS 11 |
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#define | MXC_F_I2C_INT_EN0_DATA_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_DATA_ER_POS)) |
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#define | MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS 12 |
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#define | MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS)) |
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#define | MXC_F_I2C_INT_EN0_START_ER_POS 13 |
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#define | MXC_F_I2C_INT_EN0_START_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_START_ER_POS)) |
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#define | MXC_F_I2C_INT_EN0_STOP_ER_POS 14 |
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#define | MXC_F_I2C_INT_EN0_STOP_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_STOP_ER_POS)) |
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#define | MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS 15 |
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#define | MXC_F_I2C_INT_EN0_TX_LOCK_OUT ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS)) |
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#define | MXC_F_I2C_INT_EN0_RD_ADDR_MATCH_POS 22 |
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#define | MXC_F_I2C_INT_EN0_RD_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_RD_ADDR_MATCH_POS)) |
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#define | MXC_F_I2C_INT_EN0_WR_ADDR_MATCH_POS 23 |
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#define | MXC_F_I2C_INT_EN0_WR_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_WR_ADDR_MATCH_POS)) |
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#define | MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS 0 |
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#define | MXC_F_I2C_INT_FL1_RX_OVERFLOW ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS)) |
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#define | MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS 1 |
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#define | MXC_F_I2C_INT_FL1_TX_UNDERFLOW ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS)) |
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#define | MXC_F_I2C_INT_FL1_START_POS 2 |
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#define | MXC_F_I2C_INT_FL1_START ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL1_START_POS)) |
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#define | MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS 0 |
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#define | MXC_F_I2C_INT_EN1_RX_OVERFLOW ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS)) |
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#define | MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS 1 |
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#define | MXC_F_I2C_INT_EN1_TX_UNDERFLOW ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS)) |
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#define | MXC_F_I2C_INT_EN1_START_POS 2 |
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#define | MXC_F_I2C_INT_EN1_START ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN1_START_POS)) |
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#define | MXC_F_I2C_FIFO_LEN_RX_LEN_POS 0 |
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#define | MXC_F_I2C_FIFO_LEN_RX_LEN ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_LEN_RX_LEN_POS)) |
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#define | MXC_F_I2C_FIFO_LEN_TX_LEN_POS 8 |
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#define | MXC_F_I2C_FIFO_LEN_TX_LEN ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_LEN_TX_LEN_POS)) |
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#define | MXC_F_I2C_RX_CTRL0_DNR_POS 0 |
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#define | MXC_F_I2C_RX_CTRL0_DNR ((uint32_t)(0x1UL << MXC_F_I2C_RX_CTRL0_DNR_POS)) |
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#define | MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS 7 |
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#define | MXC_F_I2C_RX_CTRL0_RX_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS)) |
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#define | MXC_F_I2C_RX_CTRL0_RX_THRESH_POS 8 |
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#define | MXC_F_I2C_RX_CTRL0_RX_THRESH ((uint32_t)(0xFUL << MXC_F_I2C_RX_CTRL0_RX_THRESH_POS)) |
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#define | MXC_F_I2C_RX_CTRL1_RX_CNT_POS 0 |
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#define | MXC_F_I2C_RX_CTRL1_RX_CNT ((uint32_t)(0xFFUL << MXC_F_I2C_RX_CTRL1_RX_CNT_POS)) |
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#define | MXC_F_I2C_RX_CTRL1_RX_FIFO_POS 8 |
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#define | MXC_F_I2C_RX_CTRL1_RX_FIFO ((uint32_t)(0xFUL << MXC_F_I2C_RX_CTRL1_RX_FIFO_POS)) |
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#define | MXC_F_I2C_TX_CTRL0_TX_PRELOAD_POS 0 |
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#define | MXC_F_I2C_TX_CTRL0_TX_PRELOAD ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_PRELOAD_POS)) |
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#define | MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS 1 |
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#define | MXC_F_I2C_TX_CTRL0_TX_READY_MODE ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS)) |
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#define | MXC_F_I2C_TX_CTRL0_TX_AMGC_AFD_POS 2 |
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#define | MXC_F_I2C_TX_CTRL0_TX_AMGC_AFD ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_AMGC_AFD_POS)) |
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#define | MXC_F_I2C_TX_CTRL0_TX_AMW_AFD_POS 3 |
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#define | MXC_F_I2C_TX_CTRL0_TX_AMW_AFD ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_AMW_AFD_POS)) |
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#define | MXC_F_I2C_TX_CTRL0_TX_AMR_AFD_POS 4 |
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#define | MXC_F_I2C_TX_CTRL0_TX_AMR_AFD ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_AMR_AFD_POS)) |
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#define | MXC_F_I2C_TX_CTRL0_TX_NACK_AFD_POS 5 |
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#define | MXC_F_I2C_TX_CTRL0_TX_NACK_AFD ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_NACK_AFD_POS)) |
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#define | MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS 7 |
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#define | MXC_F_I2C_TX_CTRL0_TX_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS)) |
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#define | MXC_F_I2C_TX_CTRL0_TX_THRESH_POS 8 |
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#define | MXC_F_I2C_TX_CTRL0_TX_THRESH ((uint32_t)(0xFUL << MXC_F_I2C_TX_CTRL0_TX_THRESH_POS)) |
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#define | MXC_F_I2C_TX_CTRL1_TX_READY_POS 0 |
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#define | MXC_F_I2C_TX_CTRL1_TX_READY ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL1_TX_READY_POS)) |
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#define | MXC_F_I2C_TX_CTRL1_TXFIFO_POS 8 |
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#define | MXC_F_I2C_TX_CTRL1_TXFIFO ((uint32_t)(0xFUL << MXC_F_I2C_TX_CTRL1_TXFIFO_POS)) |
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#define | MXC_F_I2C_FIFO_DATA_POS 0 |
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#define | MXC_F_I2C_FIFO_DATA ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_DATA_POS)) |
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#define | MXC_F_I2C_MASTER_CTRL_START_POS 0 |
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#define | MXC_F_I2C_MASTER_CTRL_START ((uint32_t)(0x1UL << MXC_F_I2C_MASTER_CTRL_START_POS)) |
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#define | MXC_F_I2C_MASTER_CTRL_RESTART_POS 1 |
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#define | MXC_F_I2C_MASTER_CTRL_RESTART ((uint32_t)(0x1UL << MXC_F_I2C_MASTER_CTRL_RESTART_POS)) |
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#define | MXC_F_I2C_MASTER_CTRL_STOP_POS 2 |
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#define | MXC_F_I2C_MASTER_CTRL_STOP ((uint32_t)(0x1UL << MXC_F_I2C_MASTER_CTRL_STOP_POS)) |
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#define | MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR_POS 7 |
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#define | MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR ((uint32_t)(0x1UL << MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR_POS)) |
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#define | MXC_F_I2C_MASTER_CTRL_MCODE_POS 8 |
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#define | MXC_F_I2C_MASTER_CTRL_MCODE ((uint32_t)(0x7UL << MXC_F_I2C_MASTER_CTRL_MCODE_POS)) |
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#define | MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP_POS 11 |
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#define | MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP ((uint32_t)(0x1UL << MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP_POS)) |
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#define | MXC_F_I2C_CLK_LO_SCL_LO_POS 0 |
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#define | MXC_F_I2C_CLK_LO_SCL_LO ((uint32_t)(0x1FFUL << MXC_F_I2C_CLK_LO_SCL_LO_POS)) |
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#define | MXC_F_I2C_CLK_HI_SCL_HI_POS 0 |
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#define | MXC_F_I2C_CLK_HI_SCL_HI ((uint32_t)(0x1FFUL << MXC_F_I2C_CLK_HI_SCL_HI_POS)) |
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#define | MXC_F_I2C_HS_CLK_HS_CLK_LO_POS 0 |
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#define | MXC_F_I2C_HS_CLK_HS_CLK_LO ((uint32_t)(0xFFUL << MXC_F_I2C_HS_CLK_HS_CLK_LO_POS)) |
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#define | MXC_F_I2C_HS_CLK_HS_CLK_HI_POS 8 |
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#define | MXC_F_I2C_HS_CLK_HS_CLK_HI ((uint32_t)(0xFFUL << MXC_F_I2C_HS_CLK_HS_CLK_HI_POS)) |
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#define | MXC_F_I2C_TIMEOUT_TO_POS 0 |
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#define | MXC_F_I2C_TIMEOUT_TO ((uint32_t)(0xFFFFUL << MXC_F_I2C_TIMEOUT_TO_POS)) |
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#define | MXC_F_I2C_DMA_TXEN_POS 0 |
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#define | MXC_F_I2C_DMA_TXEN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_TXEN_POS)) |
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#define | MXC_F_I2C_DMA_RXEN_POS 1 |
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#define | MXC_F_I2C_DMA_RXEN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_RXEN_POS)) |
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#define | MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_POS 0 |
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#define | MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR ((uint32_t)(0x3FFUL << MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_POS)) |
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#define | MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS 15 |
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#define | MXC_F_I2C_SLAVE_ADDR_EX_ADDR ((uint32_t)(0x1UL << MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS)) |
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