AD9152 no-OS driver

Supported Devices

• AD9152

Overview

The AD9152 is a dual, 16-bit digital-to-analog converter (DAC) with a sampling rate up to 2.25GSPS, suitable for generating multicarrier signals up to its Nyquist frequency. It features advanced low spurious and distortion techniques for high-quality wideband signal synthesis and integrates a JESD204B Subclass 1 interface for streamlined multichip synchronization. The DAC provides a 3- or 4-wire SPI interface, allowing for programming and readback of parameters, with an adjustable full-scale output current ranging from 4mA to 20mA. Encased in a 56-lead LFCSP, it is well-suited for applications including wireless communications, software-defined radios, and instrumentation.

Applications

• Wireless communications

  • Multicarrier LTE and GSM base stations

  • Wideband repeaters

  • Software defined radios

• Wideband communications

  • Point to point microwave radios

  • LMDS/MMDS

• Transmit diversity, multiple input/multiple output (MIMO)

• Instrumentation

• Automated test equipment

Operation Modes

Mode Name	Description	Register Configuration	Typical Use Case
DC Test Mode	Provides a DC midscale test pattern to the DACs for evaluation purposes.	Register 0x0F7, Bit 1	Testing and calibration of DAC outputs.
1x Interpolation	Operates at maximum DAC update rate without interpolation.	Register 0x112: 0x00	Max bandwidth applications needing high-speed data.
2x Interpolation	Reduces input data rate by half, applying light interpolation.	Register 0x112: 0x01	Efficient processing of standard data streams.
4x Interpolation	Further reduces input data rate, increasing interpolation for better efficacy.	Register 0x112: 0x02	For scenarios requiring optimized bandwidth usage.
8x Interpolation	Maximizes interpolation, significantly lowering input data needs.	Register 0x112: 0x03	Applications with stringent data management needs.
CDR Half-Rate	Clock and data recovery at half rate for high lane rates.	REG_CDR _OPERATING_MODE _REG_0(0x230) Bit 5	Used in high-speed serial data transmission.
Continuous Sync	Continuously checks for alignment edges using periodic SYSREF.	Register 0x03A, Bit 6	Synchronizing clocks in multi-device setups.
One Shot Sync Mode	Phase checks occur once per alignment edge.	Register 0x03A	Single event phase alignment checks.
Initial Setup Mode	Configures basic JESD204B interface parameters.	REG _JESD204B_TERM0 (0x2AA), REG_SERDES_PLL _VCO_CONTROL0 (0x28A), REG_CDR_OPERA _OPERATING_MODE _REG_0 (0x230), REG_SYNTH _ENABLE_CNTRL (0x280)	Initial JESD204B link setup for communication between converters and processors.
Synchronization Mode	Controls synchronization of the JESD204B link.	REG_SYNC_CTRL (0x03A), REG_SYNC_STATUS (0x03B)	Ensures transmitter and receiver alignment in RF and multi-ADC/DAC systems.
Data Recovery Mode	Restores raw data from physical layer to digital signal.	REG_CDR_RESET (0x206), REG_EQ_BIAS_REG (0x268)	Ensures data integrity in high-data-rate serial communication.

Device Configuration

Initialization

The core initialization function is ad9152_setup , which is responsible for allocating resources, establishing SPI communication, verifying the chip ID, and initiating the power-up sequence for the AD9152 device. It ensures necessary configurations for the digital data path, transport, and physical layer including PLL locking. Conversely, ad9152_remove handles deallocation of resources, removing the SPI descriptor and freeing memory to clean up driver usage.

Data Path Testing

Functions ad9152_short_pattern_test and ad9152_datapath_prbs_test are designed for data path testing. ad9152_short_pattern_test writes and verifies short patterns in the DAC registers to check data path integrity, whereas ad9152_datapath_prbs_test uses a pseudo-random binary sequence to test and ensure synchronization in the I and Q data channels, overall validating data handling capabilities.

Status Checking

The ad9152_status function is utilized to assess the JESD204B link status. It reads several synchronization and error-checking registers, reporting discrepancies to highlight potential issues with link stability or data integrity, thereby evaluating the operational status of the device.

Driver Initialization Example

#include <stdio.h>
#include <stdint.h>
#include "no_os_delay.h"
#include "no_os_spi.h"
#include "ad9152.h"

int32_t ret;
struct ad9152_dev *ad9152_device = NULL;
ad9152_init_param ad9152_init = {
    .spi_init = {
        .device_id      = 0,
        .max_speed_hz   = 2000000,
        .chip_select    = 1,
        .mode       = NO_OS_SPI_MODE_0,
        .platform_ops   = &xil_spi_ops,
        .extra      = &xil_spi_param
    },
    .stpl_samples = {
        { 0x12345678, 0x23456789, 0x3456789A, 0x456789AB },
        { 0x56789ABC, 0x6789ABCD, 0x789ABCDE, 0x89ABCDEF }
    },
    .interpolation    = 2,
    .prbs_type        = PRBS_TYPE_1,
    .lane_rate_kbps   = 3072000
};

ret = ad9152_setup(&ad9152_device, &ad9152_init);
if (ret)
    goto error;
printf("AD9152 initialization success\n");
ret = 0;
goto end;
error:
printf("AD9152 initialization failed\n");
ret = -1;
end:
if (ad9152_device)
    ad9152_remove(ad9152_device);