AD35XXR-EVB HDL project
Overview
The EVAL-AD3542R is an evaluation board for the AD3542R, a dual-channel, 16-bit fast precision digital-to-analog converter (DAC). The same eval board can be used to evaluate the AD3541R, the single channel part.
The EVAL-AD3552R is an evaluation board for the AD3552R, a dual-channel, 16-bit fast precision digital-to-analog converter (DAC). The same eval board can be used to evaluate the AD3551R, the single channel part. Each channel of the AD3552R is equipped with a different transimpedance amplifier: Channel 0 has a fast amplifier that achieves the optimal dynamic performance and Channel 1 has a precision amplifier that guarantees the optimal DC precision over temperature.
The boards allow testing all the output ranges of the DAC, waveform generation, power supply and reference options.
Supported boards
Supported devices
Supported carriers
Evaluation board |
Carrier |
FMC slot |
---|---|---|
FMC-LPC |
Block design
Warning
The VADJ for Zedboard must be set to 1.8V.
Block diagram
The data path and clock domains are depicted in the below diagram:
CPU/Memory interconnects addresses
The addresses are dependent on the architecture of the FPGA, having an offset added to the base address from HDL (see more at CPU/Memory interconnects addresses).
Instance |
Zynq/Microblaze |
---|---|
axi_ad35xxr_dac |
0x44A7_0000 |
axi_dac_dma |
0x44A3_0000 |
axi_clkgen |
0x44B0_0000 |
GPIOs
GPIO signal |
Direction |
HDL GPIO EMIO |
Software GPIO |
Software GPIO |
---|---|---|---|---|
(from FPGA view) |
Zynq-7000 |
Zynq MP |
||
ad35xxr_resetn |
OUT |
38 |
92 |
116 |
ad35xxr_gpio_9 |
INOUT |
37 |
91 |
115 |
ad35xxr_gpio_8 |
INOUT |
36 |
90 |
114 |
ad35xxr_gpio_7 |
INOUT |
35 |
89 |
113 |
ad35xxr_gpio_6 |
INOUT |
34 |
88 |
112 |
ad35xxr_alertn |
INOUT |
33 |
87 |
111 |
ad35xxr_ldacn |
INOUT |
32 |
86 |
110 |
Interrupts
Below are the Programmable Logic interrupts used in this project.
Instance name |
HDL |
Linux Zynq |
Actual Zynq |
---|---|---|---|
axi_dac_dma |
13 |
57 |
89 |
Building the HDL project
The design is built upon ADI’s generic HDL reference design framework. ADI distributes the bit/elf files of these projects as part of the ADI Kuiper Linux. If you want to build the sources, ADI makes them available on the HDL repository. To get the source you must clone the HDL repository, and then build the project as follows:
Linux/Cygwin/WSL
~$
cd hdl/projects/ad35xxr_evb/zed
~/hdl/projects/ad35xxr_evb/zed$
make
A more comprehensive build guide can be found in the Build an HDL project user guide.
Resources
More information
Support
Analog Devices, Inc. will provide limited online support for anyone using the reference design with ADI components via the EngineerZone FPGA reference designs forum.
For questions regarding the ADI Linux device drivers, device trees, etc. from our Linux GitHub repository, the team will offer support on the EngineerZone Linux software drivers forum.
For questions concerning the ADI No-OS drivers, from our No-OS GitHub repository, the team will offer support on the EngineerZone microcontroller No-OS drivers forum.
It should be noted, that the older the tools’ versions and release branches are, the lower the chances to receive support from ADI engineers.