AD9209-FMCA-EBZ HDL project

Overview

The AD9209-FMCA-EBZ reference design is a processor-based embedded system. This reference design works with AD9209-FMCA-EBZ/ AD9081-FMCA-EBZ (RX only) / AD9082-FMCA-EBZ (RX only) / EVAL-AD9986 (RX only) / EVAL-AD9988 (RX only).

This design consists of one receive chain. Thus, only the RX path would be used when the evaulation board is either EVAL-AD9081/AD9082/AD9986/AD9988.

The receive chain transports the captured samples from ADC to the system memory (DDR). Before transferring the data to DDR the samples are stored in a buffer implemented on block RAMs from the FPGA fabric (util_adcfifo). The space allocated in the buffer for each channel depends on the number of currently active channels. It goes up to M x 64k samples if a single channel is selected or 64k samples per channel, if all channels are selected.

All cores from the receive chain are programmable through an AXI-Lite interface.

Supported boards

• AD9209-FMCA-EBZ

• AD9081-FMCA-EBZ *

• AD9082-FMCA-EBZ *

• EVAL-AD9988 *

• EVAL-AD9986 *

Note

* - only the RX path would be used!

Supported devices

• AD9209

• AD9081

• AD9082

• AD9986

• AD9988

Supported carriers

• VCK190 on FMC0

Block design

Block diagram

The data path and clock domains are depicted in the below diagram:

Configuration modes

The block design supports configuration of parameters and scales.

We have listed a couple of examples at section Building the HDL project and the default modes for each project.

Note

The parameters for Rx links can be changed from the system_project.tcl file, located in hdl/projects/ad9209_fmca_ebz/vck190/system_project.tcl

Important

For JESD204B:

$$LaneRate=\frac{IQSampleRate\ast M\ast NP\ast \frac{10}{8}}{L}$$

For JESD204C:

$$LaneRate=\frac{IQSampleRate\ast M\ast NP\ast \frac{66}{64}}{L}$$

The following are the parameters of this project that can be configured:

• JESD_MODE: used link layer encoder mode

  • 64B66B - 64b66b link layer defined in JESD204C, uses AMD IP as Physical Layer

  • 8B10B - 8b10b link layer defined in JESD204B, uses ADI IP as Physical Layer

• RX_LANE_RATE: lane rate of the Rx link (MxFE to FPGA)

• REF_CLK_RATE: the rate of the reference clock

• RX_JESD_M: number of converters per link

• RX_JESD_L: number of lanes per link

• RX_JESD_S: number of samples per frame

• RX_JESD_NP: number of bits per sample

• RX_NUM_LINKS: number of links

• RX_KS_PER_CHANNEL: Number of samples stored in internal buffers in kilosamples per converter (M)

Clock scheme

Only the channels presented in the clocking selection are relevant. For the rest, you can either disable them or just put a divided frequency of the source clock.

Limitations

Warning

For the parameter selection, the following restrictions apply:

• NP = 8, 12, 16

• F = 1, 2, 3, 4, 6, 8

• JESD204B/C Link Rx peripheral > restrictions

CPU/Memory interconnects addresses

The addresses are dependent on the architecture of the FPGA, having an offset added to the base address from HDL (see more at CPU/Memory interconnects addresses).

Instance	Versal
rx_mxfe_tpl_core	0xA4A1_00000
axi_mxfe_rx_jesd	0xA4A9_00000
axi_mxfe_rx_dma	0xBC42_00000
mxfe_rx_data_offload	0xBC45_00000

SPI connections

SPI type	SPI manager instance	SPI subordinate	CS
PS	spi0	AD9081	0
PS	spi1	HMC7044	0

GPIOs

GPIO signal	Direction	HDL GPIO EMIO	Software GPIO
	(from FPGA view)		Versal
rxen[1:0]	OUT	57:56	135:134
rstb	OUT	55	133
hmc_sync	OUT	54	132
irqb[1:0]	IN	53:52	131:130
agc3[1:0]	IN	51:50	129:128
agc2[1:0]	IN	49:48	127:126
agc1[1:0]	IN	47:46	125:124
agc0[1:0]	IN	45:44	123:122
hmc_gpio1	INOUT	43	121
gpio[10:0]	INOUT	42:32	120:110

Interrupts

Below are the Programmable Logic interrupts used in this project.

Instance name	HDL	Linux Versal	Actual Versal
axi_mxfe_rx_dma	13	109	141
axi_mxfe_rx_jesd	11	107	139

Building the HDL project

The design is built upon ADI’s generic HDL reference design framework. ADI does not distribute the bit/elf files of these projects so they must be built from the sources available here. To get the source you must clone the HDL repository.

Example for building the project with parameters:

Linux/Cygwin/WSL

~$

cd hdl/projects/ad9209_fmca_ebz/vck190

~/hdl/projects/ad9209_fmca_ebz/vck190$

make RX_LANE_RATE=16.5 RX_JESD_L=8 \
     RX_JESD_M=4 RX_JESD_S=1 \
     RX_JESD_NP=16

The following dropdowns contain tables with the parameters that can be used to configure this project, depending on the carrier used.

Warning

For the parameter selection, the following restrictions apply:

• NP = 8, 12, 16

• F = 1, 2, 3, 4, 6, 8

• JESD204B/C Link Rx peripheral > restrictions

NP notation is equivalent with N'

Default values of the make parameters for AD9209-FMCA-EBZ

Parameter	Default
	VCK190
JESD_MODE	64B66B
RX_LANE_RATE	24.75
REF_CLK_RATE	375
RX_JESD_M	4
RX_JESD_L	8
RX_JESD_S	4
RX_JESD_NP	12
RX_NUM_LINKS	1
RX_KS_PER_CHANNEL	64

A more comprehensive build guide can be found in the Build an HDL project user guide.

Software considerations

ADC - crossbar config

Due to physical constraints, Rx lanes are reordered as described in the following table.

e.g physical lane 2 from ADC connects to logical lane 7 from the FPGA. Therefore the crossbar from the device must be set accordingly.

ADC phy Lane	FPGA Rx lane / Logical Lane
0	2
1	0
2	7
3	6
4	5
5	4
6	3
7	1

Resources

Systems related

• [Wiki] AD9081 & AD9082 & AD9988 & AD9986 Prototyping Platform User Guide

• Here you can find all the quick start guides on wiki documentation [Wiki] AD9081/AD9082/AD9986/AD9988 Quick Start Guides

• AD9209-FMCA-EBZ Quick start guide on VCK190

Hardware related

• Product datasheets:

  • AD9209

  • AD9081

  • AD9082

  • AD9988

  • AD9986

• UG-1578, Device User Guide

• UG-1829, Evaluation Board User Guide

HDL related

• AD9209_FMCA_EBZ HDL project source code

IP name	Source code link	Documentation link
AXI_DMAC	library/axi_dmac	AXI DMAC
AXI_SYSID	library/axi_sysid	AXI System ID
DATA_OFFLOAD	library/data_offload	Data Offload
SYSID_ROM	library/sysid_rom	AXI System ID
UTIL_CPACK2	library/util_pack/util_cpack2	Channel CPACK Utility
AXI_JESD204_RX	library/jesd204/axi_jesd204_rx	JESD204B/C Link Receive Peripheral
JESD204_TPL_ADC	library/jesd204/ad_ip_jesd204_tpl_adc	ADC JESD204B/C Transport Peripheral

• [Wiki] Generic JESD204B block designs

• JESD204 Interface Framework

Software related

• [Wiki] AD9081-FMCA-EBZ Linux driver wiki page applies to the AD9209-FMCA-EBZ board as well, just the RX side

• Python support:

  • AD9081 class documentation

  • Analog Devices Hardware Python Interfaces

More information

• ADI HDL User guide

Support

Analog Devices, Inc. will provide limited online support for anyone using the reference design with ADI components via the EngineerZone FPGA reference designs forum.

For questions regarding the ADI Linux device drivers, device trees, etc. from our Linux GitHub repository, the team will offer support on the EngineerZone Linux software drivers forum.

For questions concerning the ADI No-OS drivers, from our No-OS GitHub repository, the team will offer support on the EngineerZone microcontroller No-OS drivers forum.

It should be noted, that the older the tools’ versions and release branches are, the lower the chances to receive support from ADI engineers.