FMCOMMS5 HDL Project

Overview

The FMCOMMS5 is a high-speed analog module designed to showcase the AD9361 in multiple-input, multiple-output (MIMO) applications. The AD9361 is a high performance, highly integrated RF transceiver that operates from 70 MHz to 6 GHz, and supports bandwidths from less than 200 kHz to 56 MHz. The FMCOMMS5 supports dual AD9361 devices, allowing for the creation of a 4x4 MIMO system. This platform is intended to enable the prototyping and development of many software defined radio applications.

The AD9361 consists of 2 receive and 2 transmit paths (2 Rx, 2 Tx).

The only difference between AD9361 and AD9364 (1 Rx, 1 Tx) is the number of channels. Software, HDL, pinout, etc - is all the same.

The digital interface consists of 12 bits of DDR data and supports full duplex operation in all configurations up to 4x4. The transmit and receive data paths share a single clock. The data is sent or received based on the configuration (programmable) from separate transmit and to separate receive chains.

Supported boards

FMCOMMS5

Supported devices

AD9361

Supported carriers

Evaluation board	Carrier	FMC slot
FMCOMMS5	ZC702	On both FMC connectors
	ZC706	On both FMC connectors
	ZCU102	On both FMC connectors

Block design

In the receive direction, each component of the delineated data is passed to a PN monitor. The monitors validates the digital interface signal capture and timing. The data then optionally DC-filtered, corrected for I/Q offset and phase mismatches and is written to the external DDR memory via DMA. An optional off-line FFT core may be used to generate a spectrum plot.

In the transmit direction, complex I and Q signals are generated for each RF. The digital source could either be an internal DDS or from the external DDR via VDMA. The internal DDS phase and frequency are programmable.

Multi-cores operation

The core supports multiple instances of the same synchronized to a common clock. The FMCOMMS5 uses two instances of this core synchronized to a common clock. The data is recovered in each individual clock domain and transfers the data to a single clock domain. The multiple cores must all be using the same clock.

Block diagram

The data path and clock domains are depicted in the below diagram.

Clock scheme

The clocks are managed by the device and are software programmable. Please refer to the device data sheet for the various clocks within the device.

The board provides a 40MHz crystal for the AD9361.

The clock divider module will divide the input frequency by 2 when in 1R1T mode, and by 4 in 2R2T mode, to obtain the desired maximum frequency per channel: 61.44MHz.

The DMA clock frequency depends on the carrier:

when on ZC702: 150MHz
when on ZC706: 200MHz
when on ZCU102: 250MHz

Configuration modes

The AD9361 IP in this HDL project is configured to work only in LVDS interface; it supports two configuration modes:

2R2T - 2x receive and 2x transmit RF channels
1R1T - 1x receive and 1x transmit RF channel

Both support only the dual port half duplex operating mode. The maximum data rate (for combined I and Q words) is 61.44MSPS in DDR. For more details about these modes, check the AD9361 Reference Manual, Table 48 “Maximum Data Rates and Signal Bandwidths”.

CPU/Memory interconnects addresses

The addresses are dependent on the architecture of the FPGA, having an offset added to the base address from HDL (see more at CPU/Memory interconnects addresses).

Instance	Zynq/Microblaze	ZynqMP
axi_ad9361_adc_dma	0x7C40_0000	0x9C40_0000
axi_ad9361_dac_dma	0x7C42_0000	0x9C42_0000
axi_ad9361_0	0x7902_0000	0x9902_0000
axi_ad9361_1	0x7904_0000	0x9904_0000

SPI connections

The SPI signals are controlled by a separate AXI based SPI core.

SPI type	SPI manager instance	SPI subordinate	CS
PS	SPI 0	first AD9361 instance	0
PS	SPI 0	second AD9361 instance	1
PS	SPI 0	AD5355	2

GPIOs

The device control and monitor signals are interfaced to a GPIO module.

ZC706

GPIO signal	Direction	HDL GPIO EMIO	Zynq-700 GPIO
gpio_resetb_1	INOUT	59	113
gpio_ad5355_lock	INOUT	58	112
gpio_ad5355_rfen	INOUT	57	111
gpio_calsw_4_1	INOUT	56	110
gpio_calsw_3_1	INOUT	55	109
gpio_calsw_2_1	INOUT	54	108
gpio_calsw_1_1	INOUT	53	107
gpio_txnrx_1	OUT	52	106
gpio_enable_1	OUT	51	105
gpio_en_agc_1	INOUT	50	104
gpio_txnrx_0	INOUT	49	103
gpio_enable_0	INOUT	48	102
gpio_en_agc_0	INOUT	47	101
gpio_resetb_0	OUT	46	100
gpio_debug_4_1	INOUT	43	97
gpio_debug_3_1	INOUT	42	96
gpio_debug_2_1	INOUT	41	95
gpio_debug_1_1	INOUT	40	94
gpio_ctl_0[3:0]	INOUT	39:36	93:90
gpio_ctl_1[3:0]	INOUT	35:32	89:86

ZCU102

GPIO signal	Direction	HDL GPIO EMIO	Zynq MP GPIO
gpio_resetb_1	OUT	65	143
gpio_ad5355_lock	IN	64	142
gpio_ad5355_rfen	OUT	63	141
gpio_calsw_4_1	OUT	62	140
gpio_calsw_3_1	OUT	61	139
gpio_calsw_2_0	OUT	60	138
gpio_calsw_1_0	OUT	59	137
gpio_txnrx_1	OUT	58	136
gpio_enable_1	OUT	57	135
gpio_en_agc_1	OUT	56	134
gpio_txnrx_0	OUT	55	133
gpio_enable_0	OUT	54	132
gpio_en_agc_0	OUT	53	131
gpio_resetb_0	OUT	52	130
gpio_sync	OUT	51	129
gpio_debug_4_0	OUT	49	127
gpio_debug_3_0	OUT	48	126
gpio_debug_2_0	OUT	47	125
gpio_debug_1_0	OUT	46	124
gpio_ctl_1	OUT	45:42	123:120
gpio_ctl_0	OUT	41:38	119:116
gpio_status_1	IN	37:30	115:108

Interrupts

Below are the Programmable Logic interrupts used in the project.

Instance name	HDL	Linux Zynq	Actual Zynq	Linux ZynqMP	Actual ZynqMP
axi_ad9361_adc_dma	13	57	89	109	141
axi_ad9361_dac_dma	12	56	88	108	140

Building the HDL project

The design is built upon ADI’s generic HDL reference design framework. ADI distributes the bit/elf files of these projects as part of the ADI Kuiper Linux. If you want to build the sources, ADI makes them available on the HDL repository. To get the source you must clone the HDL repository.

Go to the hdl/projects/fmcomms5/$carrier location and run the make command.

Linux/Cygwin/WSL

~$

cd hdl/projects/fmcomms5/zc706

~/hdl/projects/fmcomms5/zc706$

make

A more comprehensive build guide can be found in the Build an HDL project user guide.

Resources

HDL related

FMCOMMS5 HDL project source code

IP name	Source code link	Documentation link
AXI_AD9361	library/axi_ad9361	AXI AD9361
AXI_DMAC	library/axi_dmac	AXI DMAC
AXI_SYSID	library/axi_sysid	AXI System ID
SYSID_ROM	library/sysid_rom	AXI System ID
UTIL_CPACK2	library/util_pack/util_cpack2	Channel CPACK Utility
UTIL_UPACK2	library/util_pack/util_upack2	Channel UPACK Utility
UTIL_RFIFO	library/util_rfifo	Util RFIFO
UTIL_WFIFO	library/util_wfifo	Util WFIFO
UTIL_TDD_SYNC	library/util_tdd_sync	—
UTIL_CLKDIV	library/xilinx/util_clkdiv	—

More information

ADI HDL User guide

Support

Analog Devices, Inc. will provide limited online support for anyone using the reference design with ADI components via the EngineerZone FPGA reference designs forum.

For questions regarding the ADI Linux device drivers, device trees, etc. from our Linux GitHub repository, the team will offer support on the EngineerZone Linux software drivers forum.

For questions concerning the ADI No-OS drivers, from our No-OS GitHub repository, the team will offer support on the EngineerZone microcontroller No-OS drivers forum.

It should be noted, that the older the tools’ versions and release branches are, the lower the chances to receive support from ADI engineers.