AD353XR HDL project

Overview

The AD3530R/ AD3530 are low power, 8-channel, 16-bit, buffered voltage output, digital-to-analog converters (DACs) that include a gain bit field, resulting in a full-scale output of 2.5 V (gain = 1) or 5 V (gain = 2) for a reference voltage of 2.5 V. The AD3530R has an on-chip, buffered, 2.5 V reference available at the VREF pin, capable of sourcing external loads up to +5 mA.

Each DAC channel has its own Input register and DAC register. The DAC Register stores digital code equivalent to the DAC output voltage while the Input Register acts as a temporary staging register before being passed on the DAC Register. With the LDAC function, one or more DAC registers could be updated in parallel with the data held in the Input Register. The DAC registers can also be directly written to, in which the corresponding output updates immediately without an LDAC.

The AD3530R/ AD3530 contains eight buffered voltage output DAC channels capable of sourcing and sinking up to 40 mA of current.

The AD3530R/ AD3530 contains a 27:1 multiplexer which could output a voltage on the MUX_OUT pin that is a representative of either the output voltage or output current of a chosen channel, or the internal die temperature of the device.

Applications:

Optical transceivers
Test and measurement
Industrial automation
Data acquisition systems

Supported boards

EVAL-AD3530R

Supported devices

Supported carriers

ZedBoard on FMC
Cora Z7-07S on GPIOs
DE10-Nano on GPIOs

Block design

Block diagram

The data path is depicted in the below diagram:

Hardware setup

Signal	AD353XR Testpoint	ZedBoard FMC	Cora Z7-07S GPIO	DE10-Nano GPIO
CSB(SS0)	PMOD P1	M19/FMC-LA00_P	F16	AE19
SDO(MOSI)	PMOD P2	N19/FMC-LA01_P	T12	AG15
SDI(MISO)	PMOD P3	N20/FMC-LA01_N	W15	AF18
SCK	PMOD P4	D18/FMC-CLK1_P	H15	AG18
RESETB	PMOD P8	T19/FMC-LA10_N	V13	AE20
LDACB	PMOD P9	J18/FMC_LA05_P	T14	AE17

Important

The evaluation board is powered by 5 V voltage from an external USB.

GPIOs

The Software GPIO number is calculated as follows:

Zynq-7000: if PS7 is used, then the offset is 54
All supported boards uses the same HDL GPIO EMIO Number

GPIO signal	Direction	HDL GPIO EMIO	Software GPIO
	(from FPGA view)		Zynq-7000
RESETB	OUT	33	87
LDACB	OUT	34	88

Building the HDL project

The design is built upon ADI’s generic HDL reference design framework. ADI distributes the bit/elf files of these projects as part of the ADI Kuiper Linux. If you want to build the sources, ADI makes them available on the HDL repository. To get the source you must clone the HDL repository, and then build the project as follows:

Linux/Cygwin/WSL

~$

cd hdl/projects/ad353xr/zed

~/hdl/projects/ad353xr/zed$

make

A more comprehensive build guide can be found in the Build an HDL project user guide.

Resources

HDL related

AD353XR HDL project source code

IP name	Source code link	Documentation link
AXI_CLKGEN	library/axi_clkgen	AXI CLK Generator
AXI_DMAC	library/axi_dmac	AXI DMAC
AXI_HDMI_TX	library/axi_hdmi_tx	AXI HDMI TX
AXI_I2S_ADI	library/axi_i2s_adi	—
AXI_SPDIF_TX	library/axi_spdif_tx	—
AXI_SYSID	library/axi_sysid	AXI System ID
AXI_SYSID_ROM	library/sysid_rom	AXI System ID
UTIL_I2C_MIXER	library/util_i2c_mixer	—

More information

ADI HDL User guide

Support

Analog Devices, Inc. will provide limited online support for anyone using the reference design with ADI components via the EngineerZone FPGA reference designs forum.

For questions regarding the ADI Linux device drivers, device trees, etc. from our Linux GitHub repository, the team will offer support on the EngineerZone Linux software drivers forum.

For questions concerning the ADI No-OS drivers, from our No-OS GitHub repository, the team will offer support on the EngineerZone microcontroller No-OS drivers forum.

It should be noted, that the older the tools’ versions and release branches are, the lower the chances to receive support from ADI engineers.