AXI DMAC

Analog Device AXI-DMAC DMA Controller Linux Driver.

Supported IP Cores

• AXI DMAC

Description

The AXI DMAC is a high-speed, high-throughput, general purpose DMA controller intended to be used to transfer data between system memory and other peripherals like high-speed converters.

Driver features and limitations

• Supports multiple interface types

  • AXI3/4 memory mapped

  • AXI4 Streaming

  • ADI FIFO interface

• Zero-latency transfer switch-over architecture

  • Allows continuous high-speed streaming

• Cyclic transfers

• 2D transfers

Source Code

Status

Source	Mainlined?
drivers/dma/dma-axi-dmac.c	Yes

Files

Function	File
driver	dma-axi-dmac.c
include	axi-dmac.h
Documentation	Documentation/devicetree/bindings/dma/adi,axi-dmac.yaml

Adding Linux driver support

Kernel configuration

Configure kernel with make menuconfig (alternatively use make xconfig or make qconfig)

Linux Kernel Configuration
    Device Drivers  --->
    <*>    DMA --->

            <*>   DMA Engine support  --->
        [--snip--]
        <*>   Analog Devices AXI-DMAC DMA support
        [--snip--]

Devicetree configuration

Example platform device initialization

The AXI-DMAC driver is a platform driver and can currently only be instantiated via device tree.

Required properties:

• compatible: Must be adi,axi-dmac-1.00.a.

• reg: Specification for the controllers memory mapped register map.

• interrupts: Specification for the controllers interrupt.

• clocks: Phandle and specifier to the controllers AXI interface clock

• #dma-cells: Must be 1.

Legacy-core sub-nodes (HDL before 4.3.a). Newer cores discover the source/destination configuration from the interface-description register and do not require adi,channels. The driver exposes one DMA channel, index 0.

• adi,channels: This sub-node must contain a sub-node for each DMA channel. For the channel sub-nodes the following bindings apply. They must match then configuration options of the peripheral as it was instantiated.

Required properties for adi,channels sub-node:

• #size-cells: Must be 0

• #address-cells: Must be 1

Required channel sub-node properties:

• reg: Which channel this node refers to.

• adi,source-bus-width, adi,destination-bus-width: Width of the source or destination bus in bits.

• adi,source-bus-type, adi,destination-bus-type: Type of the source or destination bus. Must be one of the following:

• 0 (AXI_DMAC_TYPE_AXI_MM): Memory mapped AXI interface

• 1 (AXI_DMAC_TYPE_AXI_STREAM): Streaming AXI interface

• 2 (AXI_DMAC_TYPE_AXI_FIFO): FIFO interface

Transfer-length width, hardware cyclic support and 2D support are detected from hardware. This driver does not parse adi,length-width, adi,cyclic or adi,2d as channel configuration properties, including for legacy cores. Only the legacy bus-description properties above are needed for HDL before 4.3.a; newer cores discover the interface configuration from hardware.

DMA clients connected to the AXI-DMAC DMA controller must use the format described in the dma.txt file using a one cell specifier. The value of the specifier refers to the DMA channel index.

Example:

Legacy-core example (HDL before 4.3.a), for a parent bus with one address and one size cell. Replace the MMIO address, interrupt controller/SPI number, clock provider/index and bus widths with the synthesized design’s values. The interrupt is level-high. Newer cores discover the channel configuration from hardware.

#include <dt-bindings/dma/axi-dmac.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
    dma: dma@7c420000 {
        compatible = "adi,axi-dmac-1.00.a";
        reg = <0x7c420000 0x10000>;
        interrupt-parent = <&gic>;
        interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&clkc 16>;
        #dma-cells = <1>;

        adi,channels {
            #size-cells = <0>;
            #address-cells = <1>;

            dma-channel@0 {
                reg = <0>;
                adi,source-bus-width = <32>;
                adi,source-bus-type = <AXI_DMAC_BUS_TYPE_AXI_MM>;
                adi,destination-bus-width = <64>;
                adi,destination-bus-type = <AXI_DMAC_BUS_TYPE_FIFO>;
            };
        };
    };
};

More Information

• Linux DMAEngine documentation