AD9834

AD9834 IIO Direct Digital Synthesis.

Supported Devices

Evaluation Boards

Reference Circuits

Description

This is a Linux industrial I/O (Linux Industrial I/O Subsystem) subsystem driver, targeting serial interface DDS controllers. The industrial I/O subsystem provides a unified framework for drivers for many different types of converters and sensors using a number of different physical interfaces (i2c, spi, etc). See Linux Industrial I/O Subsystem for more information.

Source Code

Status

Source

Mainlined?

git

Yes

Files

Function

File

driver

drivers/staging/iio/frequency/ad9834.c

include

drivers/staging/iio/frequency/ad9834.h

Adding Linux driver support

Kernel configuration

Configure kernel with make menuconfig (alternatively use make xconfig or make qconfig)

Note

The AD9834 Driver depends on CONFIG_SPI

Linux Kernel Configuration
    Device Drivers  --->
        [*] Staging drivers  --->
            <*>     Industrial I/O support --->
                --- Industrial I/O support
                -*-   Enable buffer support within IIO
                -*-   Enable triggered sampling support

                      *** Direct Digital Synthesis ***
                [--snip--]

                <*>   Analog Devices ad9833/4/ driver

                [--snip--]

Devicetree configuration

Example device-tree

In the example below, it’s assumed that spi0 is the SPI controller to which the AD983X is attached to. Typically, these are defined in the board device-tree where the AD983X is attached to.

&spi0 {
    #address-cells = <1>;
    #size-cells = <0>;
    status = "okay";

    ad9833@0{
        #clock-cells = <0>;
        compatible = "adi,ad9833";
        reg = <0>;
        spi-max-frequency = <1000000>;
        spi-cpol;
        clocks = <&osc>;
        avdd-supply = <&vcc>;
    };
};

This example also references a regulator (vcc-supply) and a clock (osc). The clock must be described to the clock framework even when physically fixed: probe requires it and frequency programming uses its rate. Describe the supply as avdd-supply.

The compabtible string can be any of the following:

  • adi,ad9833

  • adi,ad9834

  • adi,ad9837

  • adi,ad9838

Note that, the *adi,* prefix can be omitted and this still works. It is preferred to be added to avoid any potential collisions with other drivers from other vendors.

However, the voltage supply & clock can be defined via device-tree as well. See example below:

/ {
    vcc: fixedregulator@0 {
        compatible = "regulator-fixed";
        regulator-name = "fixed-supply";
        regulator-min-microvolt = <2500000>;
        regulator-max-microvolt = <2500000>;
        regulator-boot-on;
    };

    osc: oscillator {
        #clock-cells = <0>;
        compatible = "fixed-clock";
        clock-frequency = <25000000>;
    };
};

This assumes that the board has the chips & drivers to generate voltages like this & clock frequencies.

Driver testing

Use the device directory under /sys/bus/iio/devices/iio:deviceX. AD9834 exposes frequency and phase registers as out_altvoltage0_frequency, out_altvoltage1_frequency, out_altvoltage0_phase and out_altvoltage1_phase. The shared IIO scale is 1; phase codes represent 2*pi/4096 radians and have no separate phase-scale attribute.

Each and every IIO device, typically a hardware chip, has a device folder under /sys/bus/iio/devices/iio:deviceX. Where X is the IIO index of the device. Under every of these directory folders reside a set of files, depending on the characteristics and features of the hardware device in question. These files are consistently generalized and documented in the IIO ABI documentation. In order to determine which IIO deviceX corresponds to which hardware device, the user can read the name file /sys/bus/iio/devices/iio:deviceX/name. In case the sequence in which the iio device drivers are loaded/registered is constant, the numbering is constant and may be known in advance.

root:/> cd /sys/bus/iio/devices/
root:/sys/bus/iio/devices> ls
device0
root:/sys/bus/iio/devices> cd device0

root:/sys/devices/platform/bfin-spi.0/spi0.3/device0> ls -l
--w-------    1 root     root          4096 Jan  3 14:06 out_altvoltage0_frequency
--w-------    1 root     root          4096 Jan  3 14:06 out_altvoltage1_frequency
-r--r--r--    1 root     root          4096 Jan  3 14:06 out_altvoltage_scale
--w-------    1 root     root          4096 Jan  3 14:06 out_altvoltage0_frequencysymbol
--w-------    1 root     root          4096 Jan  3 14:06 out_altvoltage0_out0_wavetype
-r--r--r--    1 root     root          4096 Jan  3 14:06 out_altvoltage0_out0_wavetype_available
--w-------    1 root     root          4096 Jan  3 14:06 out_altvoltage0_out1_enable
--w-------    1 root     root          4096 Jan  3 14:06 out_altvoltage0_out1_wavetype
-r--r--r--    1 root     root          4096 Jan  3 14:06 out_altvoltage0_out1_wavetype_available
--w-------    1 root     root          4096 Jan  3 14:06 out_altvoltage0_out_enable
--w-------    1 root     root          4096 Jan  3 14:06 out_altvoltage0_phase
--w-------    1 root     root          4096 Jan  3 14:06 out_altvoltage1_phase
--w-------    1 root     root          4096 Jan  3 14:06 out_altvoltage0_phasesymbol
--w-------    1 root     root          4096 Jan  3 14:06 out_altvoltage0_pincontrol_en
-r--r--r--    1 root     root          4096 Jan  3 14:06 name
drwxr-xr-x    2 root     root             0 Jan  3 14:06 power
lrwxrwxrwx    1 root     root             0 Jan  3 14:06 subsystem -> ../../../../../bus/iio
-rw-r--r--    1 root     root          4096 Jan  3 14:06 uevent

Identify the device

root:/sys/devices/platform/bfin-spi.0/spi0.3/device0> cat name
ad9834

Basic operation

Show frequency scale

/sys/bus/iio/devices/…/ddsX_freqY_scale

Scale to be applied to ddsX_freqY in order to obtain the desired value in Hz. If shared across all frequency registers Y is not present. It is also possible X is not present if shared across all channels.

root:/sys/devices/platform/bfin-spi.0/spi0.3/device0> cat out_altvoltage_scale
1
Switch between frequency symbol 0/1

/sys/bus/iio/devices/…/ddsX_freqsymbol

Specifies the active output frequency tuning word. The value corresponds to the Y in ddsX_freqY. To exit this mode the user can write ddsX_pincontrol_freq_en or ddsX_out_enable file.

root:/sys/devices/platform/bfin-spi.0/spi0.3/device0> echo 1 > out_altvoltage0_frequencysymbol
root:/sys/devices/platform/bfin-spi.0/spi0.3/device0> echo 0 > out_altvoltage0_frequencysymbol
root:/sys/devices/platform/bfin-spi.0/spi0.3/device0>

Set frequency symbol 0/1

/sys/bus/iio/devices/…/ddsX_freqY

Stores frequency into tuning word Y. There will be more than one ddsX_freqY file, which allows for pin controlled FSK Frequency Shift Keying (ddsX_pincontrol_freq_en is active) or the user can control the desired active tuning word by writing Y to the ddsX_freqsymbol file.

root:/sys/devices/platform/bfin-spi.0/spi0.3/device0> echo 1000000 > out_altvoltage0_frequency
root:/sys/devices/platform/bfin-spi.0/spi0.3/device0> echo 500000 > out_altvoltage1_frequency

freq0 = out_altvoltage0_frequency * out_altvoltage_scale = 1000000 * 1 = 1 MHz freq1 = out_altvoltage1_frequency * out_altvoltage_scale = 500000 * 1 = 500 kHz

Phase code interpretation

The phase register is a 12-bit code. A code of 4096 would represent one full turn, so convert accepted codes 0 through 4095 to radians as code * 2*pi/4096. The shared IIO scale attribute is 1; it is not a phase-to-radians multiplier and there is no separate phase-scale file.

Set phase symbol 0/1

/sys/bus/iio/devices/…/ddsX_phaseY

Stores phase into Y. There will be more than one ddsX_phaseY file, which allows for pin controlled PSK Phase Shift Keying (ddsX_pincontrol_phase_en is active) or the user can control the desired phase Y which is added to the phase accumulator output by writing Y to the en_phase file.

root:/sys/devices/platform/bfin-spi.0/spi0.3/device0> echo 512 > out_altvoltage0_phase
root:/sys/devices/platform/bfin-spi.0/spi0.3/device0> echo 2048 > out_altvoltage1_phase

phase0 = out_altvoltage0_phase * (2*pi/4096) = 512 * 0.0015339808 = 0.7853981696 rad phase1 = out_altvoltage1_phase * (2*pi/4096) = 2048 * 0.0015339808 = PI = 3.1415926 rad

List available wavetypes

/sys/bus/iio/devices/…/ddsX_outY_wavetype_available

Lists all available output waveform options.

root:/sys/devices/platform/bfin-spi.0/spi0.3/device0> cat out_altvoltage0_out0_wavetype_available
sine triangle

Set wavetype

/sys/bus/iio/devices/…/ddsX_outY_wavetype

Specifies the output waveform. (sine, triangle, ramp, square, …) For a list of available output waveform options read available_output_modes.

root:/sys/devices/platform/bfin-spi.0/spi0.3/device0> echo sine > out_altvoltage0_out0_wavetype

Disable FSK/PSK pincontrol

/sys/bus/iio/devices/…/ddsX_pincontrol_en

ddsX_pincontrol_en: Both, the active frequency and phase is controlled by the respective phase and frequency control inputs. In case the device in question allows to independent controls, then there are dedicated files (ddsX_pincontrol_freq_en, ddsX_pincontrol_phase_en).

root:/sys/devices/platform/bfin-spi.0/spi0.3/device0> echo 0 > out_altvoltage0_pincontrol_en

Enable output 0

/sys/bus/iio/devices/…/ddsX_out_enable /sys/bus/iio/devices/…/ddsX_outY_enable

ddsX_outY_enable controls signal generation on output Y of channel X. Y may be suppressed if all channels are controlled together.

root:/sys/devices/platform/bfin-spi.0/spi0.3/device0> echo 1 > out_altvoltage0_out_enable

More Information