AXI AION Trigger

The AXI AION Trigger is an FPGA IP core driver that provides precision trigger generation and BSYNC Time-of-Flight (ToF) synchronization for multi-chip high-speed data converter systems. It is a key component in achieving synchronization between AD9084/AD9088 MxFE devices.

The driver integrates with the Linux IIO subsystem and the JESD204 framework to provide:

• 8 trigger channels with per-channel phase control

• BSYNC direction control (input or output mode)

• Internal BSYNC generation or external reference support

• Time-of-Flight calibration via IIO consumer interface to ADF4030

• JESD204 state machine integration for synchronized initialization

Supported IP Cores

• AXI AION Trigger IP v1.0.a

Description

The AXI AION Trigger IP core works in conjunction with the ADF4030 precision synchronizer and AD9084/AD9088 MxFE data converters to achieve sub-10ps multi-chip synchronization. During system initialization, the driver performs Time-of-Flight calibration to measure and compensate for PCB trace delays.

The IP core provides 8 independent trigger channels, each with programmable phase offset, allowing precise control over trigger timing relative to the BSYNC synchronization signal.

Theory of operation

BSYNC Time-of-Flight calibration

The AXI AION Trigger performs Time-of-Flight (ToF) calibration during JESD204 initialization to compensate for PCB trace delays and achieve precise multi-chip synchronization. The calibration runs only when the optional bsync IIO channel is available; otherwise the callback returns successfully without performing the sequence below:

1. Reset and Configure: The IP core is reset and configured to receive BSYNC from the ADF4030 precision synchronizer.

2. BSYNC Detection: The IP waits for BSYNC edges to be detected and captured by the internal state machine.

3. Direction Switch: The ADF4030 BSYNC output is disabled, the internal FPGA BSYNC is enabled and the FPGA is switched to output mode, then the driver waits for BSYNC ready.

4. Phase Measurement: The driver reads the ADF4030 TDC phase, in femtoseconds, after the direction switch.

5. Phase Compensation: The negative of the measured phase is applied to the ADF4030 to compensate for the path delay, ensuring BSYNC arrives at the converters at the correct time.

6. Channel Enable: The trigger channels are enabled with their configured phase offsets.

State machines

The IP core implements two state machines:

Trigger State Machine:

• idle: Waiting for trigger event

• trig_edge: Trigger edge detected

• phase_read: Reading phase value

• trig_adjust: Adjusting trigger timing

BSYNC State Machine:

• idle: Waiting for BSYNC

• bsync_edge: BSYNC edge detected

• calib: Calibration in progress

• bsync_gen: Generating BSYNC output

• bsync_alignment_error: Alignment error detected

Source Code

Status

Source	Mainlined?
drivers/iio/logic/axi-aion-trig.c	No

Files

Function	File
driver	drivers/iio/logic/axi-aion-trig.c

Adding Linux driver support

Kernel configuration

Configure kernel with make menuconfig:

Note

The AXI AION Trigger driver depends on CONFIG_IIO and CONFIG_HAS_IOMEM

Linux Kernel Configuration
    Device Drivers  --->
        Industrial I/O support --->
            Logic analyzers  --->
                <*>   Analog Devices AXI AION Trigger driver

Devicetree configuration

Basic configuration with JESD204 integration:

axi_aion_trig: axi_aion_trig@7c600000 {
    compatible = "adi,axi-aion-trig-1.0.a";
    reg = <0x7c600000 0x1000>;
    clocks = <&hmc7044 8>;
    clock-names = "device_clk";

    jesd204-device;
    #jesd204-cells = <2>;

    io-channels = <&adf4030 8>;
    io-channel-names = "bsync";
};

With JESD204 topology connections:

axi_aion_trig: axi_aion_trig@7c900000 {
    compatible = "adi,axi-aion-trig-1.0.a";
    reg = <0x7c900000 0x1000>;
    clocks = <&ltc6952 4>;
    clock-names = "device_clk";

    jesd204-device;
    #jesd204-cells = <2>;
    jesd204-inputs =
        <&adf4030 0 FRAMER_LINK_B0_RX>,
        <&adf4030 0 DEFRAMER_LINK_B0_TX>;

    io-channels = <&adf4030 8>;
    io-channel-names = "bsync";
};

Required properties

• compatible: Must be "adi,axi-aion-trig-1.0.a"

• reg: Physical base address and size of the IP core registers

• clocks: Reference to the device clock

• clock-names: Must be "device_clk"

Optional properties

• io-channels: Reference to ADF4030 IIO channel for BSYNC phase control

• io-channel-names: Must be "bsync" when io-channels is specified

• jesd204-device: JESD204 device marker

• #jesd204-cells: Number of JESD204 cells (typically 2)

• jesd204-inputs: JESD204 topology connections

Driver testing

This device can be found under /sys/bus/iio/devices/.

Use iio_info to check if the device and driver are present:

~$

iio_info

    iio:device0: axi_aion_trig
            8 channels found:
                    voltage0:  (input)
                    voltage1:  (input)
                    ...
                    voltage7:  (input)

Navigate to the device folder:

~$

cd $(grep -rw /sys/bus/iio/devices/*/name -e "axi_aion_trig" -l | xargs dirname)

IIO channel attributes

Per-channel attributes

in_voltageX_phase (read/write)

Phase offset for trigger channel X (16-bit value, 0-65535). Controls the timing of the trigger output relative to the BSYNC signal.

~$

cat in_voltage0_phase

 0

~$

echo 1000 > in_voltage0_phase

in_voltageX_en (read/write)

Enable/disable trigger channel X (0 or 1).

~$

cat in_voltage0_en

1

~$

echo 0 > in_voltage0_en

in_voltageX_status (read-only)

Status information for channel X including trigger state machine state, BSYNC state, capture status, and alignment information.

~$

cat in_voltage0_status

 trig_state=idle bsync_state=bsync_gen bsync_captured=1 bsync_alignment_error=0
 bsync_ratio=256 bsync_delay=2 bsync_ready=1

Shared attributes

in_voltage_output_enable (read/write)

Enable/disable BSYNC output mode. When enabled (1), the IP core generates BSYNC output. When disabled (0), the IP core receives external BSYNC.

in_voltage_internal_bsync_enable (read/write)

Enable/disable internal BSYNC generation.

in_voltage_frequency (read-only)

Current BSYNC frequency in Hz, calculated from the device clock and BSYNC ratio.

in_voltage_trigger_select_gpio_enable (read/write)

Enable/disable GPIO-based trigger selection.

in_voltage_trigger_now (read/write)

Write 1 to issue a manual trigger. Reads return the hardware register, which is expected to clear to 0; the driver does not force the return value to zero.

~$

echo 1 > in_voltage_trigger_now

Debug attributes

The driver provides debugfs entries for low-level debugging:

enable_debug_trig

Enable debug trigger mode.

debug_trig

Trigger debug output.

Access via debugfs:

$ cd /sys/kernel/debug/iio/iio:device0
$ echo 1 > enable_debug_trig
$ echo 1 > debug_trig

Direct register access:

$ cd /sys/kernel/debug/iio/iio:device0
$ echo 0x10 > direct_reg_access
$ cat direct_reg_access
0x3FC

More Information

Register map

Address	Name	Description
0x000C	IDENTIFICATION	IP core identification
0x0010	CONTROL	Control register (enable, reset, direction)
0x0014	DEBUG	Debug/status register
0x0018	MANUAL_TRIGGER	Manual trigger (expected to self-clear; reads return hardware state)
0x001C	TRIG_CH0_PHASE	Channel 0 phase offset
0x0020	TRIG_CH1_PHASE	Channel 1 phase offset
0x0024	TRIG_CH2_PHASE	Channel 2 phase offset
0x0028	TRIG_CH3_PHASE	Channel 3 phase offset
0x002C	TRIG_CH4_PHASE	Channel 4 phase offset
0x0030	TRIG_CH5_PHASE	Channel 5 phase offset
0x0034	TRIG_CH6_PHASE	Channel 6 phase offset
0x0038	TRIG_CH7_PHASE	Channel 7 phase offset

Control register bits

Bit(s)	Name	Description
0	BSYNC_DIRECTION	0 = output, 1 = input
1	DISABLE_INTERNAL_BSYNC	Disable internal BSYNC generation
9:2	TRIG_CHANNEL_ENABLE	Per-channel trigger enable mask
10	SW_RESET	Software reset
11	TRIG_SELECT	GPIO trigger selection
12	ENABLE_DEBUG_TRIG	Enable debug trigger mode
13	DEBUG_TRIG	Debug trigger signal
14	ENABLE_MISALIGN_CHECK	Enable misalignment checking

Related drivers

• ADF4030 - Precision synchronizer driver

• AD9084/AD9088 - MxFE data converter driver