AD9508

AD9508 1.65 GHz Clock Fanout Buffer with Output Dividers and Delay Adjust Linux Driver.

Supported Devices

• AD9508

Description

The AD9508 provides clock fanout capability in a design that emphasizes low jitter to maximize system performance. This device benefits applications like clocking data converters with demanding phase noise and low jitter requirements. There are four independent differential clock outputs, each with various types of logic levels available. Available logic types include LVDS (1.65 GHz), HSTL (1.65 GHz), and 1.8 V CMOS (250 MHz). In 1.8 V CMOS output mode, the differential output becomes two CMOS single-ended signals. The CMOS outputs are 1.8 V logic levels, regardless of the operating supply voltage. Each output has a programmable divider that can be bypassed or be set to divide by any integer up to 1024. In addition, the AD9508 supports a coarse output phase adjustment between the outputs. The device can also be pin programmed for various fixed configurations at power-up without the need for SPI or I2C programming.

Source Code

Status

Source	Mainlined?
drivers/iio/frequency/ad9508.c	No

Files

Function	File
driver	drivers/iio/frequency/ad9508.c
include	include/linux/iio/frequency/ad9508.h
include	include/dt-bindings/iio/frequency/ad9508.h

Adding Linux driver support

Kernel configuration

Configure kernel with make menuconfig (alternatively use make xconfig or make qconfig)

Note

The ad9508 Driver depends on CONFIG_SPI

Linux Kernel Configuration
    Device Drivers  --->
    <*>  Industrial I/O support --->
             Frequency Synthesizers DDS/PLL  --->
                 Clock Generator/Distribution  --->
                 <*>  Analog Devices AD9508 Clock Fanout Buffer

Devicetree configuration

The following example instantiates the AD9508 driver on SPI chip-select 3 (reg = <3>). The board must provide the input clock named clkin; the driver enables that clock during probe.

#include <dt-bindings/iio/frequency/ad9508.h>

&spi {
        clk0_ad9508: ad9508@3 {
                #address-cells = <1>;
                #size-cells = <0>;
                #clock-cells = <1>;
                compatible = "adi,ad9508";
                reg = <3>;
                spi-cpol;
                spi-cpha;

                clocks = <&ad9508_clkin>;
                clock-names = "clkin";

                spi-max-frequency = <10000000>;
                clock-output-names = "ad9508-1_out0", "ad9508-1_out1", "ad9508-1_out2", "ad9508-1_out3";
                adi,spi-3wire-enable;

                ad9508_0_c0:channel@0 {
                        reg = <0>;
                        adi,extended-name = "SYSREF";
                        adi,driver-mode = <(DRIVER_PHASE_NORMAL | DRIVER_MODE_HSTL)>;
                        adi,divider-phase = <0>;
                        adi,channel-divider = <32>;
                };

                ad9508_0_c1:channel@1 {
                        reg = <1>;
                        adi,extended-name = "PLL_REF";
                        adi,driver-mode = <(DRIVER_PHASE_NORMAL | DRIVER_MODE_HSTL)>;
                        adi,divider-phase = <0>;
                        adi,channel-divider = <1>;
                };

                ad9508_0_c2:channel@2 {
                        reg = <2>;
                        adi,extended-name = "GBTCLK";
                        adi,driver-mode = <(DRIVER_PHASE_NORMAL | DRIVER_MODE_HSTL)>;
                        adi,divider-phase = <0>;
                        adi,channel-divider = <1>;
                };

                ad9508_0_c3:channel@3 {
                        reg = <3>;
                        adi,extended-name = "DIVCLK_FMC";
                        adi,driver-mode = <(DRIVER_PHASE_NORMAL | DRIVER_MODE_HSTL)>;
                        adi,divider-phase = <0>;
                        adi,channel-divider = <1>;
                };

        };
};