AXI ADC HDL

AXI ADC HDL Linux Driver.

Supported IP Cores

Evaluation Boards

This driver supports the

Description

The AXI ADC HDL driver is the driver for Generic AXI ADC which is used on various FPGA designs. The driver is implemented as an Linux IIO driver. It’s register map can be found here: Register access

This driver is split into two parts. A control driver let’s call it SPI-ADC which configures the converter internal control registers, this part is typically instantiated via the SPI bus. (see: ad9467.c, ad9361_conv.c or ad9371_conv.c) Device probing for the data capture driver (AXI-ADC) which controls the AXI HDL core registers and the DMA, is delayed until the SPI control driver is fully probed. The device tree phandle **spibus-connected** is used to connect the capture driver with is SPI control driver. This split is required since the AXI-ADC and the SPI-ADC parts are instantiated via different busses. The AXI-ADC driver registers the IIO device, the SPI-ADC instance doesn’t. However a shared data structure (struct axiadc_converter) is used so that the methods local to the SPI-ADC driver can extend the IIO attributes provided the AXI-ADC driver. There is also a callback provided (post_setup) which calls a from the AXI-ADC into the AXI-SPI driver after the AXI-ADC is fully alive. This post setup callback is then typically used to finally configure the digital data path, test and tune the digital data interface etc.

For the AD9361 and AD9371 family of transceivers, things are a bit more differentiated. In fact these devices have a separate IIO device for the radio control portion. We call them the PHY devices. (ad9361.c and ad9371.c ) The PHY drivers are intended to be independent from our AXI-ADC capture drivers and underlying HDL designs. Therefore things related to the AXI-ADC driver are located in the ad93X1_conv.c files.

Source Code

Status

Source	Mainlined?
drivers/iio/adc/cf_axi_adc_core.c	No

Files

Function	File
driver	drivers/iio/adc/ad6676.c
driver	drivers/iio/adc/ad9208.c
driver	ad9467.c
driver	drivers/iio/adc/ad9680.c
driver	drivers/iio/adc/ad9361_conv.c
driver	drivers/iio/adc/ad9371_conv.c
driver	drivers/iio/adc/adrv9009_conv.c
core driver	drivers/iio/adc/cf_axi_adc_core.c
DMA buffer	drivers/iio/buffer/industrialio-buffer-dmaengine.c
core include	drivers/iio/adc/cf_axi_adc.h

Adding Linux driver support

Kernel configuration

Configure kernel with make menuconfig (alternatively use make xconfig or make qconfig)

Note

The AXI ADC HDL driver depends on CONFIG_SPI

Linux Kernel Configuration
    Device Drivers  --->
    <*>     Industrial I/O support --->
        --- Industrial I/O support
        -*-   Enable buffer support within IIO
        -*-   Enable triggered sampling support

              *** Analog to digital converters ***
        [--snip--]
            -*- Analog Devices High-Speed AXI ADC driver core
                <*> Analog Devices AD9208 and similar high speed ADCs
                <*> Analog Devices AD9371 RF Transceiver driver
                <*> Analog Devices ADRV9009/ADRV9008 RF Transceiver driver
                <*> Analog Devices AD6676 Wideband IF Receiver driver
                <*> Analog Devices AD9467 etc. high speed ADCs
                <*> Analog Devices AD9680 and similar high speed ADCs
        [--snip--]

Devicetree configuration

Example platform device initialization

The AXI ADC driver is a platform driver and can currently only be instantiated via device tree.

Required devicetree properties:

compatible: Should always be one of these:
- adi,axi-adc-legacy-10.0.a
- xlnx,axi-ad9234-1.00.a
- xlnx,axi-ad9250-1.00.a
- xlnx,axi-ad9434-1.00.a
- adi,axi-ad9643-6.00.a
- adi,axi-ad9361-6.00.a
- adi,axi-ad9680-1.0
- adi,axi-ad9625-1.0
- adi,axi-ad6676-1.0
- adi,axi-ad9694-1.0
- adi,axi-ad9371-rx-1.0
- adi,axi-ad9684-1.0
- adi,axi-adrv9009-rx-1.0
- adi,axi-ad9208-1.0
- For a complete list see driver source: static const struct of_device_id axiadc_of_match[]
reg: Base address and register area size. This parameter expects a register range.
spibus-connected: Phandle to the SPI device on which the AD9467/AD9643 can be found
dmas: Receive DMA controller/channel specifier. The driver creates a DMA buffer only when the HDL instance is the master (ID 0) and dmas is present.
dma-names: rx. A tx DMA entry is not used by this driver.

Example:

&fmc_spi {
    adc_ad9467: ad9467@0 {
        #address-cells = <1>;
        #size-cells = <0>;
        compatible = "adi,ad9467";
        reg = <0>;
        spi-max-frequency = <10000000>;
        clocks = <&clk_ad9517 3>;
        clock-names = "adc_clk";

        adi,spi-3wire-enable;
    };
};

&fpga_axi {
    rx_dma: rx-dmac@44a30000 {
        compatible = "adi,axi-dmac-1.00.a";
        reg = <0x44A30000 0x10000>;
        #dma-cells = <1>;
        interrupts = <0 57 0>;
        clocks = <&clkc 16>;

        adi,channels {
            #size-cells = <0>;
            #address-cells = <1>;

            dma-channel@0 {
                reg = <0>;
                adi,source-bus-width = <16>;
                adi,source-bus-type = <2>;
                adi,destination-bus-width = <64>;
                adi,destination-bus-type = <0>;
            };
        };
    };

    cf_ad9467_core_0: cf-ad9467-core-lpc@44a00000 {
        compatible = "adi,axi-adc-legacy-10.0.a";
        reg = <0x44A00000 0x10000>;
        dmas = <&rx_dma 0>;
        dma-names = "rx";

        spibus-connected = <&adc_ad9467>;
    };
};

Driver testing

Each and every IIO device, typically a hardware chip, has a device folder under /sys/bus/iio/devices/iio:deviceX. Where X is the IIO index of the device. Under every of these directory folders reside a set of files, depending on the characteristics and features of the hardware device in question. These files are consistently generalized and documented in the IIO ABI documentation. In order to determine which IIO deviceX corresponds to which hardware device, the user can read the name file /sys/bus/iio/devices/iio:deviceX/name. In case the sequence in which the iio device drivers are loaded/registered is constant, the numbering is constant and may be known in advance.

root:/> cd /sys/bus/iio/devices/
root:/sys/bus/iio/devices> ls
iio:device4  iio:trigger0

root:/sys/bus/iio/devices> cd iio:device4

root:/sys/bus/iio/devices/iio:device4> ls -l
drwxr-xr-x    2 root     root             0 Jan  1 00:00 buffer
-r--r--r--    1 root     root          4096 Jan  1 00:00 dev
-rw-r--r--    1 root     root          4096 Jan  1 00:00 in_voltage0_calibbias
-rw-r--r--    1 root     root          4096 Jan  1 00:00 in_voltage0_calibphase
-rw-r--r--    1 root     root          4096 Jan  1 00:00 in_voltage0_calibscale
-rw-r--r--    1 root     root          4096 Jan  1 00:00 in_voltage0_filter_high_pass_3db_frequency
-rw-r--r--    1 root     root          4096 Jan  1 00:00 in_voltage0_test_mode
-rw-r--r--    1 root     root          4096 Jan  1 00:00 in_voltage1_calibbias
-rw-r--r--    1 root     root          4096 Jan  1 00:00 in_voltage1_calibphase
-rw-r--r--    1 root     root          4096 Jan  1 00:00 in_voltage1_calibscale
-rw-r--r--    1 root     root          4096 Jan  1 00:00 in_voltage1_filter_high_pass_3db_frequency
-rw-r--r--    1 root     root          4096 Jan  1 00:00 in_voltage1_test_mode
-rw-r--r--    1 root     root          4096 Jan  1 00:00 in_voltage_sampling_frequency
-rw-r--r--    1 root     root          4096 Jan  1 00:00 in_voltage_scale
-r--r--r--    1 root     root          4096 Jan  1 00:00 in_voltage_scale_available
-r--r--r--    1 root     root          4096 Jan  1 00:00 in_voltage_test_mode_available
-r--r--r--    1 root     root          4096 Jan  1 00:00 name
drwxr-xr-x    2 root     root             0 Jan  1 00:00 scan_elements
lrwxrwxrwx    1 root     root             0 Jan  1 00:00 subsystem -> ../../../../bus/iio
-rw-r--r--    1 root     root          4096 Jan  1 00:00 uevent
root:/sys/bus/iio/devices/iio:device4>

Identify the device

root:/sys/bus/iio/devices/iio:device4> cat name
cf-ad9643-core-lpc

Basic operation

Show scale

Description: scale to be applied to in_voltageX_raw in order to obtain the measured voltage in millivolts.

root:/sys/bus/iio/devices/iio:device4> cat in_voltage_scale
0.026703

External Synchronization

The ADC JESD204B/C Transport Peripheral core supports the EXT_SYNC feature, allowing to synchronize multiple channels within a ADC or across multiple instances, see External synchronization section of ADC JESD204B/C Transport Peripheral. This feature can also synchronize between the ADC JESD204B/C Transport Peripheral and DAC JESD204B/C Transport Peripheral core.

There are two device attributes which allows controlling this feature: sync_start_enable and sync_start_enable_available reading the later returns the available modes which depend on HDL core synthesis parameters. The options are explained below. Reading ‘sync_start_enable’ returns either ‘arm’ while waiting for the external synchronization signal or ‘disarm’ otherwise.

arm: Setting this key will arm the trigger mechanism sensitive to an external sync signal. Once the external sync signal goes high it synchronizes channels within a ADC, and across multiple instances. This key has an effect when EXT_SYNC is present. Without EXT_SYNC, writing arm still sets the legacy ADI_SYNC bit and _available reports only arm; it is not universally a no-op.
disarm: Setting this key will disarm the trigger mechanism sensitive to an external sync signal. This key has an effect only the EXT_SYNC synthesis parameter is set.
trigger_manual: Setting this key will issue an external sync event if it is hooked up inside the fabric. This key has an effect only the EXT_SYNC synthesis parameter is set.

Example:

root@analog:/sys/bus/iio/devices/iio:device3# cat sync_start_enable_available
arm disarm trigger_manual
root@analog:/sys/bus/iio/devices/iio:device3# cat sync_start_enable
disarm
root@analog:/sys/bus/iio/devices/iio:device3# echo arm > sync_start_enable
root@analog:/sys/bus/iio/devices/iio:device3# cat sync_start_enable
arm
root@analog:/sys/bus/iio/devices/iio:device3# echo trigger_manual > sync_start_enable
root@analog:/sys/bus/iio/devices/iio:device3# cat sync_start_enable
disarm

Show available scales

root:/sys/bus/iio/devices/iio:device4> cat in_voltage_scale_available
0.031738 0.031403 0.031067 0.030731 0.030396 0.030060 0.029724 0.029388 0.029053 0.028717 0.028381 0.028046 0.027710 0.027374 0.027039 0.026703 0.026367 0.026031 0.025696 0.025360 0.025024 0.024689 0.024353 0.024017 0.023682 0.023346 0.023010 0.022675 0.022339 0.022003 0.021667 0.021332

Set ADC calibration gain

Description: in_voltage0_calibscale in_voltage1_calibscale

Set the channel calibration gain. Writing to these files will set the calibration gain for the respective channel. Valid values are in the range of approximately -1.999939..+1.999939, in 1/16384 steps.

root:/sys/bus/iio/devices/iio:device4> cat in_voltage0_calibscale
1.000000

Set ADC calibration bias

Description: in_voltage0_calibbias in_voltage1_calibbias

Set the channel calibration bias/offset. Writing to these files will set the calibration bias for the respective channel. Valid values are in the range of -32768..32767 raw-code counts. Larger values are truncated to signed 16 bits rather than rejected.

root:/sys/bus/iio/devices/iio:device4> cat in_voltage0_calibbias
0

Show available ADC test modes

Description:

Show available test modes supported by the underlying ADC. These test modes are typically used to test the high speed digital interface between the converter and interface adaptor.

root:/sys/bus/iio/devices/iio:device4> cat in_voltage_test_mode_available
off midscale_short pos_fullscale neg_fullscale checkerboard pn_long pn_short one_zero_toggle

Set ADC test mode

Description: in_voltage0_test_mode in_voltage1_test_mode

Enter test modes supported by the underlying ADC. These test modes are typically used to test the high speed digital interface between the converter and interface adaptor.

root:/sys/bus/iio/devices/iio:device4> echo one_zero_toggle > in_voltage0_test_mode
root:/sys/bus/iio/devices/iio:device4> cat in_voltage0_test_mode
one_zero_toggle
root:/sys/bus/iio/devices/iio:device4> echo off > in_voltage0_test_mode

Buffer management

root:/sys/bus/iio/devices/iio:device4/buffer> ls
bytes_per_datum          enable                   subsystem
length                   uevent
root:/sys/bus/iio/devices/iio:device4/buffer>

The Industrial I/O subsystem supports buffered data acquisition. Buffer implementation and capabilities depend on the driver. Devices with buffer support expose each buffer at /sys/bus/iio/devices/iio:deviceX/bufferY, where Y is the buffer index, starting at 0. The first buffer is additionally exposed through the legacy buffer directory, which contains its buffer-control attributes. Its scan configuration is exposed through the legacy scan_elements directory, while multi-buffer systems expose the scan attributes in the corresponding bufferY directory. Read samples from the device character node /dev/iio:deviceX; the selected buffer is determined by the active buffer configuration.

length: Get/set the number of sample sets that may be held by the buffer.
enable: Enables/disables the buffer. This file should be written last, after length and selection of scan elements.
watermark: A single positive integer specifying the maximum number of scan elements to wait for. Poll will block until the watermark is reached. Blocking read will wait until the minimum between the requested read amount or the low water mark is available. Non-blocking read will retrieve the available samples from the buffer even if there are less samples then watermark level. This allows the application to block on poll with a timeout and read the available samples after the timeout expires and thus have a maximum delay guarantee.
data_available: A read-only value indicating the bytes of data available in the buffer. In the case of an output buffer, this indicates the amount of empty space available to write data to. In the case of an input buffer, this indicates the amount of data available for reading.
length_align_bytes: Using the high-speed interface. DMA buffers may have an alignment requirement for the buffer length. Newer versions of the kernel will report the alignment requirements associated with a device through the length_align_bytes property.
scan_elements: The scan_elements directory contains interfaces for elements that will be captured for a single triggered sample set in the buffer.

root:/sys/bus/iio/devices/iio:device4/scan_elements> ls
in_voltage0_en
in_voltage0_index
in_voltage0_type
in_voltage1_en
in_voltage1_index
in_voltage1_type
root:/sys/bus/iio/devices/iio:device4/scan_elements>

in_voltageX_en / in_voltageX-voltageY_en / in_timestamp_en:: Scan element control for triggered data capture. Writing 1 will enable the scan element, writing 0 will disable it
in_voltageX_type / in_voltageX-voltageY_type / in_timestamp_type:: Describes the scan element’s representation in the buffer. The format is [be|le]:[s|u]bits/storagebits[Xrepeat]>>shift. The prefix gives byte order; s or u specifies signed (two’s complement) or unsigned data. bits is the number of meaningful bits and storagebits is the storage width. The optional repeat count describes repeated elements. After interpreting byte order, shift the storage value right by shift and mask it to bits; signed values also require sign extension. For example, be:u12/16>>1 describes an unsigned 12-bit value in big-endian 16-bit storage, shifted right by one bit. Account for alignment padding when combining enabled elements into a complete scan.
in_voltageX_index / in_voltageX-voltageY_index / in_timestamp_index:: A nonnegative integer specifying the ordering of this scan element in the buffer. Note these are not dependent on what is enabled and may not be contiguous. Thus for user-space to establish the full layout these must be used in conjunction with all _en attributes to establish which channels are present, and the relevant _type attributes to establish the data storage format.

More Information

Sub device Documentation (linked mode)

AD9208