ADF4382

The ADF4382 is a high performance, ultralow jitter, dual output integer-N and fractional-N phase-locked loop (PLL) with an integrated voltage controlled oscillator (VCO). The ADF4382 operates with a VCO frequency range of 11 GHz to 22 GHz and supports output frequencies from 687.5 MHz to 22 GHz through configurable output dividers.

The ADF4382A has a different VCO range, 11.5 GHz to 21 GHz, and supports output dividers of 1, 2 and 4. Its output bands are 11.5–21 GHz, 5.75–10.5 GHz and 2.875–5.25 GHz, respectively. The gaps between these bands are not supported; the ADF4382’s continuous output range does not apply to the ADF4382A.

The ADF4382 is commonly used as the sampling clock source for high-speed data converters such as the AD9084/AD9088 MxFE devices, providing the precision timing required for multi-chip synchronization.

Supported Devices

Description

The ADF4382 driver provides:

ADF4382 frequency synthesis from 687.5 MHz to 22 GHz, using output dividers of 1, 2, 4, 8 or 16.
ADF4382A frequency synthesis within the three output bands above, using output dividers of 1, 2 or 4. A requested frequency must map to a VCO frequency within the matched device’s limits; reference-clock and PLL configuration constraints also apply.
Dual differential outputs with independent enable control
Integrated clock provider for downstream consumers
Phase adjustment for multi-chip synchronization
Auto-alignment support for precision timing applications
Temperature monitoring

Theory of operation

Frequency synthesis

The ADF4382 uses a fractional-N PLL architecture:

Reference clock is optionally doubled and divided by R
Phase-frequency detector compares reference to feedback
VCO range: 11–22 GHz for ADF4382; 11.5–21 GHz for ADF4382A.
Output dividers provide final output frequency

The output frequency is calculated as:

fVCO = fREF × D × N / R

fREF is the reference frequency.
D is the reference doubler.
R is the reference divider.
O is the output divider.
N is the feedback divider and is given by the following:

\[N = N_{INT} + \frac{FRAC1WORD + \frac{FRAC2WORD}{MOD2WORD}}{MOD1WORD}\]

f_PFD is given by the following:

\[f_{PFD} = \frac{f_{REF} * D}{R}\]

The output frequency, f_RFOUT, produced at the output of the output divider is given by the following:

\[f_{RFOUT} = \frac{VCO}{O}\]

An example for the calculation procedure is described at “Output Frequency Calculation Procedure” in the datasheet.

Multi-chip synchronization

When used with AD9084/AD9088 MxFE devices and the ADF4030 precision synchronizer, the ADF4382 supports auto-alignment mode:

Enable auto-alignment via en_auto_align attribute
Write phase offset via phase attribute
The PLL adjusts its phase to align with the BSYNC signal from ADF4030

This enables ±10ps multi-chip synchronization across multiple converters.

Source Code

Status

Source	Mainlined?
drivers/iio/frequency/adf4382.c	No

Files

Function	File
driver	drivers/iio/frequency/adf4382.c

Adding Linux driver support

Kernel configuration

Configure kernel with make menuconfig:

Note

The ADF4382 driver depends on CONFIG_SPI and CONFIG_IIO

Linux Kernel Configuration
    Device Drivers  --->
        Industrial I/O support --->
            Frequency Synthesizers DDS/PLL  --->
                <*>   Analog Devices ADF4382 Wideband Synthesizer

Devicetree configuration

Basic configuration as clock source for AD9084:

adf4382: adf4382@0 {
    #clock-cells = <1>;
    compatible = "adi,adf4382";
    reg = <0>;
    spi-max-frequency = <1000000>;
    adi,spi-3wire-enable;
    clocks = <&clkin_125>;
    clock-names = "ref_clk";
    clock-output-names = "adf4382_out_clk";
    adi,power-up-frequency = /bits/ 64 <20000000000>;
    label = "adf4382";
    #io-channel-cells = <1>;
};

Consumer example (AD9084 using ADF4382 as clock source):

ad9084: ad9084@0 {
    compatible = "adi,ad9084";
    reg = <0>;

    /* Use ADF4382 as device clock */
    clocks = <&adf4382 0>;
    clock-names = "dev_clk";

    /* IIO channel for phase/frequency control */
    io-channels = <&adf4030 5>, <&adf4382 0>;
    io-channel-names = "bsync", "clk";
};

Required properties

compatible: Must be "adi,adf4382" or "adi,adf4382a"
reg: SPI chip select number
clocks: Reference to the reference clock input
clock-names: Must be "ref_clk"

Optional properties

adi,power-up-frequency: Initial output frequency in Hz (64-bit)
adi,ref-divider: Reference divider value
adi,charge-pump-microamp: Charge pump current in microamps
adi,bleed-word: Bleed current configuration word
adi,output-power-value: Output power level setting
adi,spi-3wire-enable: Enable 3-wire SPI mode
adi,ref-doubler-en: Enable reference frequency doubler
adi,cmos-3v3: Use 3.3V CMOS output levels
#clock-cells: Set to <1> to act as clock provider
clock-output-names: Name for the output clock
#io-channel-cells: Set to <1> to act as IIO provider

Driver testing

This device can be found under /sys/bus/iio/devices/.

Use iio_info to check if the device and driver are present:

~$

iio_info

 iio:device0: adf4382
     3 channels found:
         altvoltage0:  (output)
         altvoltage1:  (output)
         temp0:  (input)

Navigate to the device folder:

~$

cd $(grep -rw /sys/bus/iio/devices/*/name -e "adf4382" -l | xargs dirname)

IIO channel attributes

Output channels (altvoltage0, altvoltage1)

out_altvoltageX_en (read/write): Enable/disable the output channel.
out_altvoltageX_hardwaregain (read/write): Output power level setting.
out_altvoltage_phase (read/write): Signed phase adjustment in femtoseconds (shared by both output channels). Read back the quantized result.
out_altvoltage_frequency (read/write): Output frequency in Hz (shared by all channels).

~$

cat out_altvoltage_frequency

20000000000

~$

echo 19500000000 > out_altvoltage_frequency

out_altvoltage_en_auto_align (read/write): Enable/disable auto-alignment mode. Used for multi-chip synchronization with ADF4030 and AD9084/AD9088.
out_altvoltage_bleed_pol (read/write): Bleed current polarity.
out_altvoltage_coarse_current (read/write): Coarse charge pump current setting.
out_altvoltage_fine_current (read/write): Fine charge pump current setting.

Temperature channel (temp0)

in_temp0_input (read-only): Die temperature in millidegrees Celsius.

$ cat in_temp0_input
  45000

Clock provider interface

The ADF4382 registers as a clock provider, allowing downstream devices to reference it directly via devicetree:

/* In AD9084 devicetree node */
clocks = <&adf4382 0>;