ad9081

class adi.ad9081.ad9081(uri='')

Bases: rx_tx, context_manager, sync_start

AD9081 Mixed-Signal Front End (MxFE)

property adc_frequency: adc_frequency: ADC frequency in Hz

property api_version: api_version: API version

property chip_version: chip_version: Chip version information

property dac_frequency: dac_frequency: DAC frequency in Hz

property jesd204_device_status: jesd204_device_status: Device jesd204 link status information

property jesd204_device_status_check

jesd204_device_status_check: Device jesd204 link status check

Returns ‘True’ in case error conditions are detected, ‘False’ otherwise

property jesd204_fsm_ctrl: jesd204_fsm_ctrl: jesd204-fsm control

property jesd204_fsm_error: jesd204_fsm_error: jesd204-fsm error

property jesd204_fsm_paused: jesd204_fsm_paused: jesd204-fsm paused

property jesd204_fsm_resume: jesd204_fsm_resume: jesd204-fsm resume

property jesd204_fsm_state: jesd204_fsm_state: jesd204-fsm state

property loopback_mode

loopback_mode: Enable loopback mode RX->TX

When enabled JESD RX FIFO is connected to JESD TX FIFO, making the entire datasource for the TX path the RX path. No data is passed into the TX path from off-chip when 1. For this mode to function correctly the JESD configuration between RX and TX must be identical and only use a single link.

property path_map: path_map: Map of channelizers both coarse and fine to individual driver channel names

property pfilt_config

property powerdown

powerdown: Powerdown and reset the chip

Support for dynamic powerdown. Writing device attribute powerdown with ‘Yy1Nn0’, or [oO][NnFf] for “on” and “off”, will either stop the jesd204 fsm, reset the device and power down an optional regulator (vdd), or do the opposite in reverse order.

property rx_channel_6dB_digital_gains: rx_channel_6dB_digital_gains: Enable 6dB of gain per FDDC

property rx_channel_nco_frequencies: rx_channel_nco_frequencies: Receive path fine DDC NCO frequencies

property rx_channel_nco_phases: rx_channel_nco_phases: Receive path fine DDC NCO phases

property rx_main_6dB_digital_gains: rx_main_6dB_digital_gains: Enable 6dB of gain per CDDC

property rx_main_ffh_gpio_mode_enable: rx_main_ffh_gpio_mode_enable: Enablles GPIO controlled frequency hopping

property rx_main_ffh_mode: rx_main_ffh_mode: ADC FFH mode. Options are: instantaneous_update, synchronous_update_by_transfer_bit, synchronous_update_by_gpio

property rx_main_ffh_trig_hop_en: rx_main_ffh_trig_hop_en: Enable triggered hopping for CDDC NCO

property rx_main_nco_ffh_index: rx_main_nco_ffh_index: Receive path coarse DDC NCO index in range [0,15]

property rx_main_nco_ffh_select: rx_main_nco_ffh_select: Receive path coarse DDC NCO select in range [0,15]

property rx_main_nco_frequencies: rx_main_nco_frequencies: Receive path coarse DDC NCO frequencies

property rx_main_nco_phases: rx_main_nco_phases: Receive path coarse DDC NCO phases

property rx_nyquist_zone: rx_nyquist_zone: ADC nyquist zone. Options are: odd, even

property rx_sample_rate: rx_sampling_frequency: Sample rate after decimation

property rx_test_mode: rx_test_mode: NCO Test Mode

set_tx_dac_full_scale_current(value): tx_dac_full_scale_current: Set full scale current of DACs. This value is in microamps.

property tx_channel_nco_frequencies: tx_channel_nco_frequencies: Transmit path fine DUC NCO frequencies

property tx_channel_nco_gain_scales: tx_channel_nco_gain_scales Transmit path fine DUC NCO gain scale

property tx_channel_nco_phases: tx_channel_nco_phases: Transmit path fine DUC NCO phases

property tx_channel_nco_test_tone_en: tx_channel_nco_test_tone_en: Transmit path fine DUC NCO test tone enable

property tx_channel_nco_test_tone_scales: tx_channel_nco_test_tone_scales: Transmit path fine DUC NCO test tone scale

property tx_dac_en: tx_dac_en: Enable DACs

property tx_dac_full_scale_current

property tx_ddr_offload

tx_ddr_offload: Enable DDR offload

When true the DMA will pass buffers into the BRAM FIFO for data repeating. This is necessary when operating at high DAC sample rates. This can reduce the maximum buffer size but data passed to DACs in cyclic mode will not underflow due to memory bottlenecks.

property tx_main_ffh_frequency: tx_main_ffh_frequency: Transmitter fast frequency hop frequency. This will set The NCO frequency of the NCO selected from the bank defined by tx_main_ffh_index

property tx_main_ffh_gpio_mode_enable: tx_main_ffh_gpio_mode_enable: Enablles GPIO controlled frequency hopping

property tx_main_ffh_index: tx_main_ffh_index: Transmitter fast frequency hop NCO bank index in range [0,30]

property tx_main_ffh_mode: tx_main_ffh_mode: Set hop transition mode of NCOs Options are: phase_continuous, phase_incontinuous, and phase_coherent

property tx_main_nco_ffh_select: tx_main_nco_ffh_select: Transmit path coarse DDC NCO select in range [0,30]

property tx_main_nco_frequencies: tx_main_nco_frequencies: Transmit path coarse DUC NCO frequencies

property tx_main_nco_phases: tx_main_nco_phases: Transmit path coarse DUC NCO phases

property tx_main_nco_test_tone_en: tx_main_nco_test_tone_en: Transmit path coarse DUC NCO test tone enable

property tx_main_nco_test_tone_scales: tx_main_nco_test_tone_scales: Transmit path coarse DUC NCO test tone scale

property tx_sample_rate: tx_sampling_frequency: Sample rate before interpolation

write_pfilt_config(value): Load a new PFILT configuration file Input is path to PFILT configuration file. Please see driver documentation about PFILT generation and limitations