| ▼CTB | |
| ►CTB_Registers | Registers, Bit Masks and Bit Positions for the CTB Peripheral Module |
| Register Offsets | CTB Peripheral Register Offsets from the CTB Base Peripheral Address |
| CTB_CRYPTO_CTRL | Crypto Control Register |
| CTB_CIPHER_CTRL | Cipher Control Register |
| CTB_HASH_CTRL | HASH Control Register |
| CTB_CRC_CTRL | CRC Control Register |
| CTB_DMA_SRC | Crypto DMA Source Address |
| CTB_DMA_DEST | Crypto DMA Destination Address |
| CTB_DMA_CNT | Crypto DMA Byte Count |
| CTB_CRYPTO_DIN | Crypto Data Input. Data input can be written to this register instead of using the DMA. This register writes to the FIFO. This register occupies four successive words to allow the use of multi-store instructions. Words can be written to any location, they will be placed in the FIFO in the order they are written. The endian swap input control bit affects this register |
| CTB_CRYPTO_DOUT | Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on the algorithm. For block cipher modes, this register holds the result of most recent encryption or decryption operation. These registers are affected by the endian swap bits |
| CTB_CRC_POLY | CRC Polynomial. The polynomial to be used for Galois Field calculations (CRC or LFSR) should be written to this register. This register is affected by the MSB control bit |
| CTB_CRC_VAL | CRC Value. This is the state for the Galois Field. This register holds the result of a CRC calculation or the current state of the LFSR. This register is affected by the MSB control bit |
| CTB_CRC_PRNG | Pseudo-Random Number Generator. Output of the Galois Field shift register. This holds the resulting pseudo-random number if entropy is disabled or true random number if entropy is enabled |
| CTB_HAM_ECC | Hamming ECC Register |
| CTB_CIPHER_INIT | Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits |
| CTB_CIPHER_KEY | Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter key lengths. This register is affected by the endian swap input control bits |
| CTB_HASH_DIGEST | This register holds the calculated hash value. This register is affected by the endian swap bits |
| CTB_HASH_MSG_SZ | Message Size. This register holds the lowest 32-bit of message size in bytes |
| CTB_A_LENGTH_0 | .AAD Length Register 0 |
| CTB_A_LENGTH_1 | .AAD Length Register 1 |
| CTB_PLD_LENGTH_0 | .PLD Length Register 0 |
| CTB_PLD_LENGTH_1 | .LENGTH |
| CTB_TAGMIC | TAG/MIC Registers |
| CTB_SCA_CN | SCA Control 0 Register |
| CTB_SCA_ACN | SCA Advanced Control Register |
| CTB_SCA_ST | SCA Status Register |
| CTB_SCA_PPX_ADDR | PPX Coordinate Data Pointer Register |
| CTB_SCA_PPY_ADDR | PPY Coordinate Data Pointer Register |
| CTB_SCA_PPZ_ADDR | PPZ Coordinate Data Pointer Register |
| CTB_SCA_PQX_ADDR | PQX Coordinate Data Pointer Register |
| CTB_SCA_PQY_ADDR | PQY Coordinate Data Pointer Register |
| CTB_SCA_PQZ_ADDR | PQZ Coordinate Data Pointer Register |
| CTB_SCA_RDSA_ADDR | SCA RDSA Address Register |
| CTB_SCA_RES_ADDR | SCA Result Address Register |
| CTB_SCA_OP_BUFF_ADDR | SCA Operation Buffer Address Register |
| CTB_SCA_MODDATA | SCA Modulo Data Input Register |
| ▼Direct Memory Access (DMA) | |
| ►DMA_Registers | Registers, Bit Masks and Bit Positions for the DMA Peripheral Module |
| Register Offsets | DMA Peripheral Register Offsets from the DMA Base Peripheral Address |
| DMA_CN | DMA Control Register |
| DMA_INTR | DMA Interrupt Register |
| DMA_CFG | DMA Channel Configuration Register |
| DMA_ST | DMA Channel Status Register |
| DMA_SRC | Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD |
| DMA_DST | Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD |
| DMA_CNT | DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered |
| DMA_SRC_RLD | Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition |
| DMA_DST_RLD | Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition |
| DMA_CNT_RLD | DMA Channel Count Reload Register |
| ▼Flash Controller (FLC) | |
| ►FLC_Registers | Registers, Bit Masks and Bit Positions for the FLC Peripheral Module |
| Register Offsets | FLC Peripheral Register Offsets from the FLC Base Peripheral Address |
| FLC_FLSH_ADDR | Flash Write Address |
| FLC_FLSH_CLKDIV | Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 MHz clock for Flash controller |
| FLC_FLSH_CN | Flash Control Register |
| FLC_FLSH_INT | Flash Interrupt Register |
| FLC_FLSH_DATA | Flash Write Data |
| FLC_ACNTL | Access Control Register. Writing the ACTRL register with the following values in the order shown, allows read and write access to the system and user Information block: pflc-actrl = 0x3a7f5ca3; pflc-actrl = 0xa1e34f20; pflc-actrl = 0x9608b2c1. When unlocked, a write of any word will disable access to system and user information block. Readback of this register is always zero |
| ▼General-Purpose Input/Output (GPIO) | |
| ►Port and Pin Definitions | |
| Port Definitions | |
| Pin Definitions | |
| ►GPIO_Registers | Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module |
| Register Offsets | GPIO Peripheral Register Offsets from the GPIO Base Peripheral Address |
| GPIO_EN0 | GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one GPIO pin on the associated port |
| GPIO_EN0_SET | GPIO Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN to 1, without affecting other bits in that register |
| GPIO_EN0_CLR | GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN to 0, without affecting other bits in that register |
| GPIO_OUT_EN | GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one GPIO pin in the associated port |
| GPIO_OUT_EN_SET | GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT_EN to 1, without affecting other bits in that register |
| GPIO_OUT_EN_CLR | GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0, without affecting other bits in that register |
| GPIO_OUT | GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the associated port. This register can be written either directly, or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers |
| GPIO_OUT_SET | GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT to 1, without affecting other bits in that register |
| GPIO_OUT_CLR | GPIO Output Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT to 0, without affecting other bits in that register |
| GPIO_IN | GPIO Input Register. Read-only register to read from the logic states of the GPIO pins on this port |
| GPIO_INT_MOD | GPIO Interrupt Mode Register. Each bit in this register controls the interrupt mode setting for the associated GPIO pin on this port |
| GPIO_INT_POL | GPIO Interrupt Polarity Register. Each bit in this register controls the interrupt polarity setting for one GPIO pin in the associated port |
| GPIO_IN_EN | GPIO Input Enable |
| GPIO_INT_EN | GPIO Interrupt Enable Register. Each bit in this register controls the GPIO interrupt enable for the associated pin on the GPIO port |
| GPIO_INT_EN_SET | GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits in that register |
| GPIO_INT_EN_CLR | GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_EN to 0, without affecting other bits in that register |
| GPIO_INT_STAT | GPIO Interrupt Status Register. Each bit in this register contains the pending interrupt status for the associated GPIO pin in this port |
| GPIO_INT_CLR | GPIO Status Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits in that register |
| GPIO_WAKE_EN | GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup enable for the associated GPIO pin in this port |
| GPIO_WAKE_EN_SET | GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in that register |
| GPIO_WAKE_EN_CLR | GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other bits in that register |
| GPIO_INT_DUAL_EDGE | GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual edge mode for the associated GPIO pin in this port |
| GPIO_PDPU_SEL0 | GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port |
| GPIO_PDPU_SEL1 | GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port |
| GPIO_EN1 | GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port |
| GPIO_EN1_SET | GPIO Alternate Function Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN1 to 1, without affecting other bits in that register |
| GPIO_EN1_CLR | GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN1 to 0, without affecting other bits in that register |
| GPIO_DS_SEL0 | GPIO Drive Strength Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode |
| GPIO_DS_SEL1 | GPIO Drive Strength 1 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode |
| GPIO_PSSEL | GPIO Pull Select Mode |
| ▼I2C | |
| ►I2C_Registers | Registers, Bit Masks and Bit Positions for the I2C Peripheral Module |
| Register Offsets | I2C Peripheral Register Offsets from the I2C Base Peripheral Address |
| I2C_CN | Control Register0 |
| I2C_ST | Status Register |
| I2C_INT0 | Interrupt Status Register |
| I2C_INTEN0 | Interrupt Enable Register |
| I2C_INT1 | Interrupt Status Register 1 |
| I2C_INTEN1 | Interrupt Staus Register 1 |
| I2C_FIFO | FIFO Configuration Register |
| I2C_RXCFG | Receive Control Register 0 |
| I2C_RX | Receive Control Register 1 |
| I2C_TXCFG | Transmit Control Register 0 |
| I2C_TX | Transmit Control Register 1 |
| I2C_DATA | Data Register |
| I2C_MCN | Master Control Register |
| I2C_CKL | Clock Low Register |
| I2C_CKH | Clock high Register |
| I2C_TO | Timeout Register |
| I2C_DMA | DMA Register |
| I2C_SLA | Slave Address Register |
| ▼ICC | |
| ►ICC_Registers | Registers, Bit Masks and Bit Positions for the ICC Peripheral Module |
| Register Offsets | ICC Peripheral Register Offsets from the ICC Base Peripheral Address |
| ICC_CACHE_ID | Cache ID Register |
| ICC_MEMCFG | Memory Configuration Register |
| ICC_CACHE_CTRL | Cache Control and Status Register |
| ICC_INVALIDATE | Invalidate All Registers |
| ▼Low Power (LP) | |
| ►PWRSEQ_Registers | Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral Module |
| Register Offsets | PWRSEQ Peripheral Register Offsets from the PWRSEQ Base Peripheral Address |
| PWRSEQ_LPCN | Low Power Control Register |
| PWRSEQ_LPWKST0 | Low Power I/O Wakeup Status Register 0. This register indicates the low power wakeup status for GPIO0 |
| PWRSEQ_LPWKEN0 | Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup functionality for GPIO0 |
| PWRSEQ_LPWKST1 | Low Power I/O Wakeup Status Register 1. This register indicates the low power wakeup status for GPIO1 |
| PWRSEQ_LPWKEN1 | Low Power I/O Wakeup Enable Register 1. This register enables low power wakeup functionality for GPIO1 |
| PWRSEQ_LPPWKST | Low Power Peripheral Wakeup Status Register |
| PWRSEQ_LPMEMSD | Low Power Memory Shutdown Control |
| Assertion Checks for Debugging | Assertion checks for debugging |
| Delay Utility Functions | Asynchronous delay routines based on the SysTick Timer |
| Error Codes | A list of common error codes used by the API |
| Exclusive Access Locks | Lock functions to obtain and release a variable for exclusive access. These functions are marked interrupt safe if they are interrupt safe |
| System Configuration (MXC_SYS) | |
| ▼Serial Flash Emulator (SFE) | |
| ►SFE_Registers | Registers, Bit Masks and Bit Positions for the SFE Peripheral Module |
| Register Offsets | SFE Peripheral Register Offsets from the SFE Base Peripheral Address |
| SFE_CFG | SFE Configuration Register |
| SFE_HFSA | SFE Host Flash Start Address Register |
| SFE_HRSA | SFE Host RAM Start Address Register |
| SFE_SFDP_SBA | SFE Discoverable Parameter System Base Register |
| SFE_FLASH_SBA | Flash System Base Address Register |
| SFE_FLASH_STA | Flash System Top Address Register |
| SFE_RAM_SBA | RAM System Base Address Register |
| SFE_RAM_STA | RAM System Top Address Register |
| ▼Security Monitor(SMON) | |
| ►SMON_Registers | Registers, Bit Masks and Bit Positions for the SMON Peripheral Module |
| Register Offsets | SMON Peripheral Register Offsets from the SMON Base Peripheral Address |
| SMON_EXTSCN | External Sensor Control Register |
| SMON_INTSCN | Internal Sensor Control Register |
| SMON_SECALM | Security Alarm Register |
| SMON_SECDIAG | Security Diagnostic Register |
| SMON_SECST | Security Monitor Status Register |
| SMON_SDBE | Security Monitor Self Destruct Byte |
| ▼SPI | |
| ►SPI_Registers | Registers, Bit Masks and Bit Positions for the SPI Peripheral Module |
| Register Offsets | SPI Peripheral Register Offsets from the SPI Base Peripheral Address |
| SPI_DATA32 | Register for reading and writing the FIFO |
| SPI_DATA16 | Register for reading and writing the FIFO |
| SPI_DATA8 | Register for reading and writing the FIFO |
| SPI_MSTR_CNTL | Register for controlling SPI peripheral |
| SPI_TRNMT_SIZE | Register for controlling SPI peripheral |
| SPI_STATIC_CONFIG | Register for controlling SPI peripheral |
| SPI_SS_TIME | Register for controlling SPI peripheral/Slave Select Timing |
| SPI_CLK_CONFIG | Register for controlling SPI clock rate |
| SPI_DMA | Register for controlling DMA |
| SPI_INT_FL | Register for reading and clearing interrupt flags. All bits are write 1 to clear |
| SPI_INT_EN | Register for enabling interrupts |
| SPI_WAKE_FL | Register for wake up flags. All bits in this register are write 1 to clear |
| SPI_WAKE_EN | Register for wake up enable |
| SPI_STAT | SPI Status register |
| ▼Timer (TMR) | |
| ►TMR_Registers | Registers, Bit Masks and Bit Positions for the TMR Peripheral Module |
| Register Offsets | TMR Peripheral Register Offsets from the TMR Base Peripheral Address |
| TMR_INTR | Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the associated interrupt |
| TMR_CN | Timer Control Register |
| ▼UART | |
| ►UART_Registers | Registers, Bit Masks and Bit Positions for the UART Peripheral Module |
| Register Offsets | UART Peripheral Register Offsets from the UART Base Peripheral Address |
| UART_CTRL | Control Register |
| UART_STAT | Status Register |
| UART_INT_EN | Interrupt Enable Register |
| UART_INT_STAT | Interrupt Status Flags |
| UART_BAUD0 | Baud rate register. Integer portion |
| UART_BAUD1 | Baud rate register. Decimal Setting |
| UART_DATA | FIFO Data buffer |
| UART_DMA | DMA Configuration |
| ▼Watchdog Timer (WDT) | |
| ►WDT_Registers | Registers, Bit Masks and Bit Positions for the WDT Peripheral Module |
| Register Offsets | WDT Peripheral Register Offsets from the WDT Base Peripheral Address |
| WDT_CTRL | Watchdog Timer Control Register |
| WDT_RST | Watchdog Timer Reset Register |
| ▼AES_Registers | Registers, Bit Masks and Bit Positions for the AES Peripheral Module |
| Register Offsets | AES Peripheral Register Offsets from the AES Base Peripheral Address |
| ▼AESKEYS_Registers | Registers, Bit Masks and Bit Positions for the AESKEYS Peripheral Module |
| Register Offsets | AESKEYS Peripheral Register Offsets from the AESKEYS Base Peripheral Address |
| ▼FCR_Registers | Registers, Bit Masks and Bit Positions for the FCR Peripheral Module |
| Register Offsets | FCR Peripheral Register Offsets from the FCR Base Peripheral Address |
| FCR_FCTRL0 | Register 0 |
| ▼GCR_Registers | Registers, Bit Masks and Bit Positions for the GCR Peripheral Module |
| Register Offsets | GCR Peripheral Register Offsets from the GCR Base Peripheral Address |
| GCR_SYSCTRL | System Control |
| GCR_RST0 | Reset |
| GCR_CLKCTRL | Clock Control |
| GCR_PM | Power Management |
| GCR_PCLKDIV | Peripheral Clock Divider |
| GCR_PCLKDIS0 | Peripheral Clock Disable |
| GCR_MEMCTRL | Memory Clock Control Register |
| GCR_MEMZ | Memory Zeroize Control |
| GCR_SYSST | System Status Register |
| GCR_RST1 | Reset 1 |
| GCR_PCLKDIS1 | Peripheral Clock Disable |
| GCR_EVENTEN | Event Enable Register |
| GCR_REVISION | Revision Register |
| GCR_SYSIE | System Status Interrupt Enable Register |
| GCR_ECCERR | ECC Error Register |
| GCR_ECCCED | ECC Not Double Error Detect Register |
| GCR_ECCIE | ECC IRQ Enable Register |
| GCR_ECCADDR | ECC Error Address Register |
| ▼MCR_Registers | Registers, Bit Masks and Bit Positions for the MCR Peripheral Module |
| Register Offsets | MCR Peripheral Register Offsets from the MCR Base Peripheral Address |
| MCR_ECCEN | ECC Enable Register |
| ▼SIR_Registers | Registers, Bit Masks and Bit Positions for the SIR Peripheral Module |
| Register Offsets | SIR Peripheral Register Offsets from the SIR Base Peripheral Address |
| SIR_SISTAT | System Initialization Status Register |
| SIR_ERRADDR | Read-only field set by the SIB block if a CRC error occurs during the read of the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 1) |
| SIR_FSTAT | Funcstat register |
| SIR_SFSTAT | Secfuncstat register |
| ▼TRNG_Registers | Registers, Bit Masks and Bit Positions for the TRNG Peripheral Module |
| Register Offsets | TRNG Peripheral Register Offsets from the TRNG Base Peripheral Address |
| TRNG_CN | TRNG Control Register |
| TRNG_ST | Data. The content of this register is valid only when RNG_IS = 1. When TRNG is disabled, read returns 0x0000 0000 |
| TRNG_DATA | Data. The content of this register is valid only when RNG_IS = 1. When TRNG is disabled, read returns 0x0000 0000 |
1.9.4 
