SPI Engine Offload Module

The SPI Engine Offload peripheral allows to store a SPI Engine command and SDO data stream in a RAM or ROM module. The command stream is executed when the trigger signal is asserted. This allows the execution of SPI transactions with a very short delay in reaction to a event.

Files

Name	Description
library/spi_engine/spi_engine_offload/spi_engine_offload.v	Verilog source for the peripheral.
library/spi_engine/spi_engine_offload/spi_engine_offload_ip.tcl	TCL script to generate the Vivado IP-integrator project for the peripheral.

Configuration Parameters

Name	Description	Default Value	Choices/Range
ASYNC_SPI_CLK	If set to 1 the ctrl_clk and spi_clk are assumed to be asynchronous.	False
ASYNC_TRIG	Asynchronous trigger.	False
CMD_MEM_ADDRESS_WIDTH	Configures the size of the command stream storage. The size is 2**CMD_MEM_ADDR_WIDTH entries.	4	From 1 to 16.
SDO_MEM_ADDRESS_WIDTH	Configures the size of the SDO data stream storage. The size is 2**SDO_MEM_ADDR_WIDTH entries.	4	From 1 to 16.
DATA_WIDTH	Shift register’s data width.	8	From 8 to 256.
NUM_OF_SDI	Number of MISO lines.	1	From 1 to 8.

Signal and Interface Pins

spi_engine_ctrl

SPI Engine Control Interface controller. SPI Engine Control stream that contains commands and data.

Physical Port	Logical Port	Direction	Dependency
cmd_ready	cmd_ready	in
cmd_valid	cmd_valid	out
cmd	cmd_data	out [15:0]
sdo_data_ready	sdo_ready	in
sdo_data_valid	sdo_valid	out
sdo_data	sdo_data	out [7:0]
sdi_data_ready	sdi_ready	out
sdi_data_valid	sdi_valid	in
sdi_data	sdi_data	in [7:0]
sync_ready	sync_ready	out
sync_valid	sync_valid	in
sync_data	sync_data	in [7:0]

spi_engine_offload_ctrl

SPI Engine Offload Control Interface subordinate. Control interface which allows to re-program the stored command and SDO data stream.

Physical Port	Logical Port	Direction	Dependency
ctrl_cmd_wr_en	cmd_wr_en	in
ctrl_cmd_wr_data	cmd_wr_data	in [15:0]
ctrl_sdo_wr_en	sdo_wr_en	in
ctrl_sdo_wr_data	sdo_wr_data	in [7:0]
ctrl_enable	enable	in
ctrl_enabled	enabled	out
ctrl_mem_reset	mem_reset	in
status_sync_ready	sync_ready	in
status_sync_valid	sync_valid	out
status_sync_data	sync_data	out [7:0]

offload_sdi

Streaming AXI controller Output stream of the received SPI data.

Physical Port	Logical Port	Direction	Dependency
offload_sdi_valid	TVALID	out
offload_sdi_ready	TREADY	in
offload_sdi_data	TDATA	out [7:0]

Ports

Physical Port	Direction	Dependency	Description
ctrl_clk	in		The spi_engine_offload_ctrl signals are synchronous to this clock. Bus spi_engine_offload_ctrl is synchronous to this clock domain.
spi_clk	in		The spi_engine_ctrl signals, offload_sdi signals and trigger are synchronous to this clock. Bus spi_engine_ctrl_offload_sdi is synchronous to this clock domain.
spi_resetn	in		Synchronous active low reset - Resets the internal state machine of the core. Bus spi_engine_ctrl_offload_sdi is synchronous to this reset signal.
trigger	in		When asserted the stored command and data stream is send out on the spi_engine_ctrl interface.