SPI Engine Interconnect Module#

The SPI Engine Interconnect allows connecting multiple SPI Engine Control Interface managers to a single SPI Engine Control Interface subordinate. This enables multiple command stream generators to connect to a single SPI Engine Execution Module and consequential give them access to the same SPI bus. The interconnect modules take care of properly arbitrating between the different command streams.

Combining multiple command stream generators in a design and connecting them to a single execution module allows for the creation of flexible and efficient designs using standard components.

Files#

Name	Description
library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v	Verilog source for the peripheral.
library/spi_engine/spi_engine_interconnect/spi_engine_interconnect_ip.tcl	TCL script to generate the Vivado IP-integrator project for the peripheral.

Configuration Parameters#

Name	Description	Default Value	Choices/Range
`DATA_WIDTH`	Data width of the parallel SDI/SDO data interfaces.	`8`	From 8 to 256.
`NUM_OF_SDI`	Number of SDI lines on the physical SPI interface.	`1`	From 1 to 8.

Signal and Interface Pins#

m_ctrl

SPI Engine Control Interface manager. Connects to the control interface subordinate.

Physical Port	Logical Port	Direction
`m_cmd_ready`	`cmd_ready`	in
`m_cmd_valid`	`cmd_valid`	out
`m_cmd_data`	`cmd_data`	out [15:0]
`m_sdo_ready`	`sdo_ready`	in
`m_sdo_valid`	`sdo_valid`	out
`m_sdo_data`	`sdo_data`	out [7:0]
`m_sdi_ready`	`sdi_ready`	out
`m_sdi_valid`	`sdi_valid`	in
`m_sdi_data`	`sdi_data`	in [7:0]
`m_sync_ready`	`sync_ready`	out
`m_sync_valid`	`sync_valid`	in
`m_sync`	`sync_data`	in [7:0]

s0_ctrl

SPI Engine Control Interface subordinate. Connects to the first control interface manager.

Physical Port	Logical Port	Direction
`s0_cmd_ready`	`cmd_ready`	out
`s0_cmd_valid`	`cmd_valid`	in
`s0_cmd_data`	`cmd_data`	in [15:0]
`s0_sdo_ready`	`sdo_ready`	out
`s0_sdo_valid`	`sdo_valid`	in
`s0_sdo_data`	`sdo_data`	in [7:0]
`s0_sdi_ready`	`sdi_ready`	in
`s0_sdi_valid`	`sdi_valid`	out
`s0_sdi_data`	`sdi_data`	out [7:0]
`s0_sync_ready`	`sync_ready`	in
`s0_sync_valid`	`sync_valid`	out
`s0_sync`	`sync_data`	out [7:0]

s1_ctrl

SPI Engine Control Interface subordinate. Connects to the second control interface manager.

Physical Port	Logical Port	Direction
`s1_cmd_ready`	`cmd_ready`	out
`s1_cmd_valid`	`cmd_valid`	in
`s1_cmd_data`	`cmd_data`	in [15:0]
`s1_sdo_ready`	`sdo_ready`	out
`s1_sdo_valid`	`sdo_valid`	in
`s1_sdo_data`	`sdo_data`	in [7:0]
`s1_sdi_ready`	`sdi_ready`	in
`s1_sdi_valid`	`sdi_valid`	out
`s1_sdi_data`	`sdi_data`	out [7:0]
`s1_sync_ready`	`sync_ready`	in
`s1_sync_valid`	`sync_valid`	out
`s1_sync`	`sync_data`	out [7:0]

Ports

Physical Port	Direction	Dependency	Description
`clk`	in		A signals of the module are synchronous to this clock. Buses `m_ctrl`, `s0_ctrl`, `s1_ctrl` are synchronous to this clock domain.
`resetn`	in		Synchronous active-low reset. Resets the internal state of the module. Buses `m_ctrl`, `s0_ctrl`, `s1_ctrl` are synchronous to this reset signal.

Theory of Operation#

The SPI Engine Interconnect module has multiple SPI Engine Control Interface subordinate ports and a single SPI Engine Control Interface manager port. It can be used to connect multiple command stream generators to a single command execution engine. Arbitration between the streams is done on a priority basis, streams with a lower index have higher priority. This means if commands are present on two streams arbitration will be granted to the one with the lower index. Once arbitration has been granted the port it was granted to stays in control until it sends a SYNC command. When the interconnect module sees a SYNC command arbitration will be re-evaluated after the SYNC command has been completed. This makes sure that once a SPI transaction consisting of multiple commands has been started it is able to complete without being interrupted by a higher priority stream.