SPI Engine Execution Module

The SPI Engine Execution IP core is the heart of the SPI Engine framework. It is responsible for handling a SPI Engine control stream and translates it into low-level SPI bus transactions.

Files

Name	Description
library/spi_engine/spi_engine_execution/spi_engine_execution.v	Verilog source for the peripheral.
library/spi_engine/spi_engine_execution/spi_engine_execution_ip.tcl	TCL script to generate the Vivado IP-integrator project for the peripheral.

Configuration Parameters

Name	Description	Default Value	Choices/Range
`NUM_OF_CS`	Number of chip-select signals for the SPI bus (min: 1, max: 8).	`1`	From 1 to 8.
`DEFAULT_SPI_CFG`	Reset configuration value for the SPI Configuration Register	`0`	0, 1, 2, 3
`DEFAULT_CLK_DIV`	Reset configuration value for the Prescaler Configuration Register	`0`	From 0 to 255.
`DATA_WIDTH`	Data width of the parallel data stream. Will define the transaction’s granularity. Supported values: 8/16/24/32	`8`	From 8 to 32.
`NUM_OF_SDI`	Number of multiple SDI lines, (min: 1, max: 8)	`1`	From 1 to 8.
`SDO_DEFAULT`	MOSI default level.	`'b0`	“0”, “1”
`ECHO_SCLK`	Echoed SCLK.	`False`
`SDI_DELAY`	Delay MISO latching.	`False`

Signal and Interface Pins

ctrl

SPI Engine Control Interface subordinate. SPI Engine Control stream that contains commands and data for the execution module.

Physical Port	Logical Port	Direction
`cmd_ready`	`cmd_ready`	out
`cmd_valid`	`cmd_valid`	in
`cmd`	`cmd_data`	in [15:0]
`sdo_data_ready`	`sdo_ready`	out
`sdo_data_valid`	`sdo_valid`	in
`sdo_data`	`sdo_data`	in [7:0]
`sdi_data_ready`	`sdi_ready`	in
`sdi_data_valid`	`sdi_valid`	out
`sdi_data`	`sdi_data`	out [7:0]
`sync_ready`	`sync_ready`	in
`sync_valid`	`sync_valid`	out
`sync`	`sync_data`	out [7:0]

spi

SPI Bus Interface controller. Low-level SPI bus interface that is controlled by peripheral.

Physical Port	Logical Port	Direction
`sclk`	`sclk`	out
`sdi`	`sdi`	in [0:0]
`sdo`	`sdo`	out
`sdo_t`	`sdo_t`	out
`three_wire`	`three_wire`	out
`cs`	`cs`	out [0:0]

Ports

Physical Port	Direction	Dependency	Description
`clk`	in		All other signals are synchronous to this clock. Buses `ctrl`, `spi` are synchronous to this clock domain.
`resetn`	in		Resets the internal state machine of the core. Buses `ctrl`, `spi` are synchronous to this reset signal.
`active`	out		Indicates whether the peripheral is currently active and processing commands.
`echo_sclk`	in	`ECHO_SCLK`

Theory of Operation

The SPI Engine Execution module implements the physical access to the SPI bus. It implements a small but powerful programmable state machine that translates a SPI Engine command stream into low-level SPI bus access.

Communication with a command stream generator happens via the ctrl interface and the low-level SPI access is handled on the spi interface. The active signal is asserted as long as the peripheral is busy executing incoming commands.

Internally the SPI Engine execution module consists of an instruction encoder that translates the incoming commands into an internal control signal, a multi-function counter and compares unit that is responsible for handling the timing and a shift register which holds the received and transmitted SPI data.

The module has an optional programmable pre-scaler register that can be used to divide the external clock to the counter and compare unit.