AXI CLK Generator#

The AXI CLK Generator IP core is a software programmable clock generator.

Features#

The top module, library/axi_clkgen/axi_clkgen.v, instantiates a MMCM wrapper, the register map and the AXI handling interface.

The ad_mmcm_drp is a wrapper over MMCM, which can instantiate a Virtex 6 MMCM or 7 Series MMCM. Detailed information regarding the 7 Series MMCM can be found in AMD Xilinx UG472 and UG953.

The register map allows resetting the MMCM, changing the clock source, checking the status of the MMCM lock and controlling the DRP interface.

Files#

Name	Description
library/axi_clkgen/axi_clkgen.v	Verilog source for the peripheral.

Block Diagram#

Configuration Parameters#

Note

Both pulse width and pulse offset are in number of clock cycles.

Name	Description	Default Value	Choices/Range
`ID`	Core ID should be unique for each IP in the system	`0`
`FPGA_TECHNOLOGY`	Fpga Technology.	`0`	Unknown (0), 7series (1), ultrascale (2), ultrascale+ (3), versal (4)
`FPGA_FAMILY`	Fpga Family.	`0`	Unknown (0), artix (1), kintex (2), virtex (3), zynq (4), versalprime (5), versalaicore (6), versalpremium (7)
`SPEED_GRADE`	Speed Grade.	`0`	Unknown (0), -1 (10), -1L (11), -1H (12), -1HV (13), -1LV (14), -2 (20), -2L (21), -2LV (22), -2MP (23), -2LVC (24), -2LVI (25), -3 (30)
`DEV_PACKAGE`	Dev Package.	`0`	Unknown (0), rf (1), fl (2), ff (3), fb (4), hc (5), fh (6), cs (7), cp (8), ft (9), fg (10), sb (11), rb (12), rs (13), cl (14), sf (15), ba (16), fa (17), fs (18), fi (19), vs (20), ls (21)
`FPGA_VOLTAGE`	Fpga Voltage.	`0`	From 0 to 5000.
`CLKSEL_EN`	Clksel En.	`0`
`CLKIN_PERIOD`	Default clock period for CLKIN1	`5`
`CLKIN2_PERIOD`	Default clock period for CLKIN2	`5`
`VCO_DIV`	DIVCLK_DIVIDE MMCM parameter	`11`
`VCO_MUL`	CLKFBOUT_MULT_F MMCM parameter	`49`
`CLK0_DIV`	CLKOUT0_DIVIDE_F MMCM parameter	`6`
`CLK0_PHASE`	CLKOUT0_PHASE MMCM parameter	`0`
`CLK1_DIV`	CLKOUT1_DIVIDE MMCM parameter	`6`
`CLK1_PHASE`	CLKOUT1_PHASE MMCM parameter	`0`
`ENABLE_CLKIN2`	Enable secondary clock input.	`False`
`ENABLE_CLKOUT1`	Enable secondary clock output.	`False`

Interface#

s_axi

AXI Slave Memory Map interface

Physical Port	Logical Port	Direction
`s_axi_awaddr`	`AWADDR`	in [15:0]
`s_axi_awprot`	`AWPROT`	in [2:0]
`s_axi_awvalid`	`AWVALID`	in
`s_axi_awready`	`AWREADY`	out
`s_axi_wdata`	`WDATA`	in [31:0]
`s_axi_wstrb`	`WSTRB`	in [3:0]
`s_axi_wvalid`	`WVALID`	in
`s_axi_wready`	`WREADY`	out
`s_axi_bresp`	`BRESP`	out [1:0]
`s_axi_bvalid`	`BVALID`	out
`s_axi_bready`	`BREADY`	in
`s_axi_araddr`	`ARADDR`	in [15:0]
`s_axi_arprot`	`ARPROT`	in [2:0]
`s_axi_arvalid`	`ARVALID`	in
`s_axi_arready`	`ARREADY`	out
`s_axi_rdata`	`RDATA`	out [31:0]
`s_axi_rresp`	`RRESP`	out [1:0]
`s_axi_rvalid`	`RVALID`	out
`s_axi_rready`	`RREADY`	in

s_axi_aclk

Physical Port	Logical Port	Direction	Dependency
`s_axi_aclk`	`CLK`	in

s_axi_aresetn

Physical Port	Logical Port	Direction	Dependency
`s_axi_aresetn`	`RST`	in

clk

Reference clock 1

Physical Port	Logical Port	Direction	Dependency
`clk`	`CLK`	in

clk2

Reference clock 2

Physical Port	Logical Port	Direction	Dependency
`clk2`	`CLK`	in	`ENABLE_CLKIN2`

clk_*

Output clock, 1 and 2

Physical Port	Logical Port	Direction	Dependency
`*`	`CLK`	out

Ports

Physical Port	Direction	Dependency	Description

Register Map#

Clock Generator (axi_clkgen) register map

DWORD	BYTE	Reg Name				Description
		BITS	Field Name	Type	Default Value	Description
`0x10`	`0x40`	`RSTN`				Interface Control & Status
		`[1:1]`	`MMCM_RSTN`	`RW`	`0x0`	MMCM reset (required for DRP access). Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.
		`[0:0]`	`RSTN`	`RW`	`0x0`	Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.
`0x11`	`0x44`	`CLK_SEL`				Clock Select
		`[0:0]`	`CLK_SEL`	`RW`	`0x0`	Select betwen CLKIN1 (0x0) or CLKIN2 (0x1) input clock for the MMCM
`0x17`	`0x5c`	`MMCM_STATUS`				MMCM Status
		`[0:0]`	`MMCM_LOCKED`	`RO`	`0x0`	LOCKED status of the MMCM
`0x1c`	`0x70`	`DRP_CNTRL`				ADC Interface Control & Status
		`[28:28]`	`DRP_RWN`	`RW`	`0x0`	DRP read (0x1) or write (0x0) select (does not include GTX lanes).
		`[27:16]`	`DRP_ADDRESS`	`RW`	`0x000`	DRP address, designs that contain more than one DRP accessible primitives have selects based on the most significant bits (does not include GTX lanes).
		`[15:0]`	`DRP_WDATA`	`RW`	`0x0000`	DRP write data (does not include GTX lanes).
`0x1d`	`0x74`	`DRP_STATUS`				MMCM Status
		`[17:17]`	`MMCM_LOCKED`	`RO`	`0x0`	LOCKED status of the MMCM
		`[16:16]`	`DRP_STATUS`	`RO`	`0x0`	If set indicates busy (access pending). The read data may not be valid if this bit is set (does not include GTX lanes).
		`[15:0]`	`DRP_RDATA`	`RO`	`0x0000`	DRP read data (does not include GTX lanes).
`0x50`	`0x140`	`FPGA_VOLTAGE`				FPGA device voltage information
		`[15:0]`	`FPGA_VOLTAGE`	`RO`	`0x0000`	The voltage of the FPGA device in mv

Access Type	Name	Description
RW	Read-write	Reads will return the current register value. Writes will change the current register value.
RO	Read-only	Reads will return the current register value. Writes have no effect.