AXI System ID#

s_axis_axi_aclks_axi_aresetnsys_rom_datapr_rom_datarom_addraxi_sysid

The System ID solution is comprised of 2 IP cores: the AXI System ID which provides the AXI Lite interface and System ID ROM which acts as a ROM and contains the data. Together, they provide the user with information regarding the conditions in which the hardware system was built. The System ID information is used to provide information about the system’s bit file, to facilitate future debugging actions. This information will be stored internally in a ROM and will be made available to the system via the AXI Lite interface.

Files#

Name

Description

library/axi_sysid/axi_sysid.v

Verilog source for the peripheral.

Block Diagram#

AXI System ID block diagram

Configuration Parameters#

AXI System ID#

Name

Description

Default Value

Choices/Range

ROM_WIDTH

ROM width.

32

ROM_ADDR_BITS

Number of address bits.

9

System ID ROM#

Name

Description

Default Value

Choices/Range

ROM_WIDTH

ROM width.

32

ROM_ADDR_BITS

Number of address bits.

6

PATH_TO_FILE

Location of ROM init file.

path_to_mem_init_file

Interface#

AXI System ID#

Physical Port

Logical Port

Direction

Dependency

s_axi_awaddr AWADDR

in [15:0]

s_axi_awprot AWPROT

in [2:0]

s_axi_awvalid AWVALID

in

s_axi_awready AWREADY

out

s_axi_wdata WDATA

in [31:0]

s_axi_wstrb WSTRB

in [3:0]

s_axi_wvalid WVALID

in

s_axi_wready WREADY

out

s_axi_bresp BRESP

out [1:0]

s_axi_bvalid BVALID

out

s_axi_bready BREADY

in

s_axi_araddr ARADDR

in [15:0]

s_axi_arprot ARPROT

in [2:0]

s_axi_arvalid ARVALID

in

s_axi_arready ARREADY

out

s_axi_rdata RDATA

out [31:0]

s_axi_rresp RRESP

out [1:0]

s_axi_rvalid RVALID

out

s_axi_rready RREADY

in

Physical Port

Logical Port

Direction

Dependency

s_axi_aclk CLK

in

Physical Port

Logical Port

Direction

Dependency

s_axi_aresetn RST

in

Physical Port

Direction

Dependency

Description

sys_rom_data

in [31:0]

Data input from System ROM.

pr_rom_data

in [31:0]

Data input from PR ROM.

rom_addr

out [8:0]

ROM address output.

System ID ROM#

Physical Port

Logical Port

Direction

Dependency

clk CLK

in

Physical Port

Direction

Dependency

Description

rom_addr

in [5:0]

Address input.

rom_data

out [31:0]

Data output.

Clocking#

The IP core runs on the AXI clock and requires a frequency of 100MHz.

Register Map#

DWORD

BYTE

Reg Name

Description

BITS

Field Name

Type

Default Value

Description

0x0 0x0 VERSION

Version of the peripheral. Follows semantic versioning. Current version 1.1.61.

[31:16] VERSION_MAJOR RO 0x0001

[15:8] VERSION_MINOR RO 0x00

[7:0] VERSION_PATCH RO 0x61

0x1 0x4 PERIPHERAL_ID

[31:0] PERIPHERAL_ID RO

‘’ID’’

Value of the ID configuration parameter.

0x2 0x8 SCRATCH

[31:0] SCRATCH RW 0x00000000

Scratch register useful for debug.

0x3 0xc IDENTIFICATION

[31:0] IDENTIFICATION RO 0x53594944

Peripheral identification (‘S’, ‘Y’, ‘I’, ‘D’).

0x200 0x800 SYSROM_START

[31:0] SYSROM_START RO

Start of register space for System ROM. Initialized at synthesis.

0x400 0x1000 PRROM_START

[31:0] SYSROM_START RO

Start of register space for partial reconfiguration block ROM. Initialized at synthesis.

Access Type

Name

Description

RO

Read-only

Reads will return the current register value. Writes have no effect.

RW

Read-write

Reads will return the current register value. Writes will change the current register value.

Theory of Operation#

The System ID consists of a system of 2 or more IP cores where one provides access to the AXI Lite interface, and the other behaves as a ROM. There can be more than one ROM IP cores if required. The information contained by the ROM will be generated and written at synthesis and will provide details as revealed further in this document.

Once written, these contents cannot be changed, only read. These ROMs will be 32 bits wide with a fixed length of 512 lines for the System ROM (2KiB). The secondary PR ROM will generally be smaller.

Data Format#

Common Header#

Field size

Field

Value

Data format

4B *

Common Header Format Version

31:16 - reserved, write as 0000h ; 15:0 - format version number

hex

4B *

Internal Use Area Starting Offset

00000000h indicates that this area is not present

hex

4B *

Board Area Starting Offset

00000000h indicates that this area is not present

hex

4B *

Product Info Area Starting Offset

00000000h indicates that this area is not present

hex

4B *

System Custom String Area Starting Offset

00000000h indicates that this area is not present

hex

4B

PR custom string area (ROM2)

00000000h indicates that this area is not present

hex

9 x 4B

Padding

00000000h

hex

4B *

Checksum

hex

Internal Use Area#

Field size

Field

Data format

28B *

Git branch

hex

44B *

Git tag (sha)

hex

4B *

Git clean check

hex

4B *

Vadj check

hex

12B *

Build date/time as seconds since 1970-01-01_00:00:00 (UTC)

hex

4B *

Padding (00000000h)

hex

4B *

Checksum

hex

* = These fields are MANDATORY

Common Header: The Common Header is mandatory for all System ID Information Device implementations. It holds version information for the overall information format specification and offsets to the other information areas. The other areas may or may not be present based on the application of the device. A field is specified as ‘Null’ or ‘not present’ when the Common Header has a value of 00h for the starting offset for that area.

Common Header Format Version: This area version information regarding the Common Header.

Internal Use Area: This area contains information describing the circumstances in which the project was built.

Product Info Area: Contains the name of the targeted product. Data converted from ASCII to hex. Size: Variable, 32 Bytes default.

System Custom String: Character string written by the user. Data converted from ASCII to hex. Size: Variable, 32 Bytes default.

Board Info Area: This area provides the name of the platform that the project is targeting. Data converted from ASCII to hex. Size: 32 Bytes.

System Custom String Area: This area provides a region where a custom string supplied by the user will be written to. This will be stored in ROM1, inside the system bit. Data converted from ASCII to hex. Size: Variable, 32 Bytes default.

PR Custom String Area: This area provides a region where a custom string provided by the user will be written to. This will be stored in ROM2, inside the PR bit where available. Data converted from ASCII to hex.

Working with the Core#

The System ID solution is automatically placed into a project by the Tcl code ADI uses to build projects. It is instantiated in two stages, first in the “Common” bd.tcl of each of the supported FPGA boards and second in the system_bd.tcl of each project.

The information written to the System ID ROM(s) is obtained from Vivado in the early stages of project building. It is at this point that the user can choose the information that will be written to the “Custom String” areas.

set sys_cstring "sys rom custom string placeholder"
sysid_gen_sys_init_file $sys_cstring