AD7606X-FMCZ HDL project#

Overview#

The AD7606 is a 8-/6-/4-Channel DAS with 16-Bit, Bipolar Input, Simultaneous Sampling ADC. Each part contains analog input clamp protection, a second-order antialiasing filter, a track-and-hold amplifier, a 16-bit charge redistribution successive approximation analog-to-digital converter (ADC), a flexible digital filter, a 2.5 V reference and reference buffer, and high speed serial and parallel interfaces. The AD7606 operate from a single 5 V supply and can accommodate ±10 V and ±5 V true bipolar input signals while sampling at throughput rates up to 200 kSPS for all channels. The input clamp protection circuitry can tolerate voltages up to ±16.5 V. The AD7606 has 1 MΩ analog input impedance regardless of sampling frequency. The single supply operation, on-chip filtering, and high input impedance eliminate the need for driver op amps and external bipolar supplies.

The AD7606C is a directly pin replacement (software and hardware) for both AD7608 and AD7609, with higher input impedance, throughput rate and extended temperature range with additional features such as 16/18-bit sample size, system gain/offset/phase calibration, sensor disconnect detection, lower Vdrive operation, diagnostics, additional oversampling ratios and per channel analog input range selection with bipolar differential, bipolar single-ended and unipolar single-ended options.

The EVAL-AD7606B-FMCZ and EVAL-AD7606C-18 evaluation boards are designed to help users to easily evaluate the features of AD7606B, AD7606C-16 and AD7606C-18 analog-to-digital converters (ADCs).

Supported boards#

Supported devices#

Supported carriers#

Block design#

The data path of the HDL design is simple as follows:

  • the parallel interface is controlled by the axi_ad7606x IP core

  • the serial interface is controlled by the SPI_Engine Framework

  • data is written into memory by a DMA (axi_dmac core)

  • all the control pins of the device are driven by GPIOs

Block diagram#

The data path and clock domains are depicted in the below diagrams:

AD7606x_FMCZ serial interface#

AD7606X_FMC using the serial interface block diagram

AD7606x_FMCZ parallel interface#

AD7606X_FMC using the parallel interface block diagram

Configuration modes#

The INTF configuration parameter defines the interface type (Serial or Parallel). By default it is set to 0. Depending on the required interface mode, some hardware modifications need to be done on the board and/or make command:

In case of the PARALLEL interface:

make INTF=0

In case of the SERIAL interface:

make INTF=1

Note

This switch is a hardware switch. Please rebuild the design if the variable has been changed.

  • JP5 - Position A - Serial interface

  • JP5 - Position B - Parallel interface

The DEV_CONFIG configuration parameter defines the device which will be used: - Options: 0 - AD7606B, 1 - AD7606C-16, 2 - AD7606C-18. By default it is set to 0.

The NUM_OF_SDI configuration parameter defines the number of SDI lines used: - Options: 1, 2, 4, 8. By default is set to 8.

The EXT_CLK configuration parameter defines the external clock option for the ADC clock: - Options: 0 - No, 1 - Yes. By default is set to 0.

Jumper setup#

Jumper/Solder link

Default Position

Description

JP1

A

The STBY pin is tied to VDRIVE

JP2

A

12V supply from the carrier

JP3

A

3.3V supply from the ADP7118

JP4

A

±10V range is selected

JP5

A

Serial interface

JP6

B

The internal reference is disabled, and the external reference is selected. P5 must be inserted if using the on-board U1 device

JP7

B

Connects the V1- line to the J5 SMB connector

JP8,JP10

A

Bypasses the amplifier mezzanine card

JP9,JP11

A

Bypasses the amplifier mezzanine card

JP12

B

Connects the V2- line to the J6 SMB connector

JP13

B

Connects the V3- line to the J7 SMB connector

JP14

B

Connects the V4- line to the J8 SMB connector

P13

Inserted

Connects the V5- line to ground

P14

Inserted

Connects the V8- line to ground

P15

Inserted

Connects the V6- line to ground

P16

Inserted

Connects the V7- line to ground

S1

On

Controls the OS0, OS1, and OS2 pins

CPU/Memory interconnects addresses#

The addresses are dependent on the architecture of the FPGA, having an offset added to the base address from HDL (see more at HDL Architecture).

Instance

Address

axi_ad7606x_dma

0x44A3_0000

spi_clkgen

0x44A7_0000

ad7606_pwm_gen

0x44B0_0000

spi_ad7616_axi_regmap **

0x44A0_0000

axi_ad7606x *

0x44A0_0000

Legend

  • * instantiated only for INTF=0 (parallel interface)

  • ** instantiated only for INTF=1 (serial interface)

I2C connections#

I2C type

I2C manager instance

Alias

Address

I2C subordinate

PL

iic_fmc

axi_iic_fmc

0x4162_0000

PL

iic_main

axi_iic_main

0x4160_0000

SPI connections#

SPI type

SPI manager instance

SPI subordinate

CS

PL

axi_spi_engine

AD7606

0

GPIOs#

The Software GPIO number is calculated as follows:

  • Zynq-7000: if PS7 is used, then offset is 54

GPIO signal

Direction

HDL GPIO EMIO

Software GPIO

(from FPGA view)

Zynq-7000

adc_serpar

OUT

39

93

adc_refsel *

OUT

38

92

adc_first_data **

IN

38

92

adc_reset

OUT

37

91

adc_stby

OUT

36

90

adc_range

OUT

35

89

adc_os

OUT

34-32

88-86

Legend

  • * instantiated only for INTF=0 (parallel interface)

  • ** instantiated only for INTF=1 (serial interface)

Interrupts#

Below are the Programmable Logic interrupts used in this project.

Instance name

HDL

Linux Zynq

Actual Zynq

axi_ad7606_dma

13

57

89

spi_ad7606 **

12

56

88

Legend

  • * instantiated only for INTF=0 (parallel interface)

  • ** instantiated only for INTF=1 (serial interface)

Building the HDL project#

The design is built upon ADI’s generic HDL reference design framework. ADI does not distribute the bit/elf files of these projects so they must be built from the sources available here. To get the source you must clone the HDL repository, and then build the project as follows:.

Linux/Cygwin/WSL

1user@analog:~$ cd hdl/projects/ad7606x_fmc/zed
2user@analog:~/hdl/projects/ad7606x_fmc/zed$ make DEV_CONFIG=2 INTF=0

The result of the build, if parameters were used, will be in a folder named by the configuration used:

if the following command was run

make DEV_CONFIG=2 INTF=0

then the folder name will be:

DEVCONFIG2_INTF0

A more comprehensive build guide can be found in the Build a HDL project user guide.

Connections and hardware changes#

Warning

The following hardware changes are required:

Depending on the required interface mode, some hardware modifications need to be done.

  • JP5 - A - Serial interface

  • JP5 - B - Parallel interface

  • JP7, JP12, JP13, JP14 - B - Differential operation

Resources#

More information#

Support#

Analog Devices, Inc. will provide limited online support for anyone using the reference design with ADI components via the EngineerZone FPGA reference designs forum.

For questions regarding the ADI Linux device drivers, device trees, etc. from our Linux GitHub repository, the team will offer support on the EngineerZone Linux software drivers forum.

For questions concerning the ADI No-OS drivers, from our No-OS GitHub repository, the team will offer support on the EngineerZone microcontroller No-OS drivers forum.

It should be noted, that the older the tools’ versions and release branches are, the lower the chances to receive support from ADI engineers.