Channel CPACK Utility#

The channel CPACK utility core is meant to allow one or more channels to be enabled by software without any padding. This allows full usage of the DMA bandwidth without any overhead. This core normally works with an ADC and DMA modules. The ADC interface is channel based (one interface per each ADC channel) and consists of enable, valid and data signals. The DMA interface is a single FIFO interface consisting of valid and data signals. The enable signals are usually controlled by software. The core simply packs the ADC data of the individual channels into a single data bus, as defined by the ADC enables.

Features#

  • Supports Altera and AMD Xilinx devices

  • Supports up to 64 channels

  • Supports configurable channel data width

Files#

Name

Description

library/util_pack/util_cpack2/util_cpack2.v

Verilog source for the peripheral.

Configuration Parameters#

Name

Description

Default Value

Choices/Range

NUM_OF_CHANNELS

Number of Channels.

4

SAMPLES_PER_CHANNEL

Samples per Channel.

1

SAMPLE_DATA_WIDTH

Sample Width.

16

Interface#

Physical Port

Logical Port

Direction

Dependency

packed_fifo_wr_en EN

out

packed_fifo_wr_data DATA

out [63:0]

packed_fifo_wr_overflow OVERFLOW

in

Physical Port

Direction

Dependency

Description

clk

in

Bus packed_fifo_wr is synchronous to this clock domain.

reset

in

Bus packed_fifo_wr is synchronous to this reset signal.

fifo_wr_en

in

Indicates that at least one payload from fifo_wr_data_* is valid.

fifo_wr_overflow

out

packed_sync

out

enable_*

in

Indicates the status of the channel, if asserted the channel is active.

fifo_wr_data_*

in [15:0]

ADC data bus from the ADC core.

Detailed Description#

The core “collects” samples from the ADC interface and passes it to the DMA (or any other sink module), the data flow is controlled by the ADC. This is best explained through some examples. Let’s consider a 4 channel ADC with a channel data width of 32 bits. The ADC core provides two 16-bit samples on its output for all channels when the valid is asserted. The DMA interface, in this case, is an interleaved 8 samples (128 bits) stream. This is because irrespective of the ADC channel data width, the software always sees data as “samples interleaved”. The same data set may received by the DMA core with a channel width of 128 bits or 16 bits.

../../_images/cpack_4channel.svg

Four channel enabled (4’b1111)#

../../_images/cpack_3channel.svg

Three channel enabled (4’b1110)#

../../_images/cpack_2channel.svg

Two channel enabled (4’b1100)#