ad9084

AD9084 is a tiled chip with 2 halves or sides. The control interfaces are unified but the DMA and DDS controls are split into multiple methods. This is similar to ADRV9002 and its split DMA modes. There are multiple rx and tx methods to control the DMA and DDS for each side of the chip. The rx (and rx1) and tx (and tx1) methods are used to control the DMA and DDS for the first side of the chip. The rx2 and tx2 methods are used to control the DMA and DDS for the second side of the chip.

class adi.ad9084.ad9084(uri='', rx1_device_name='axi-ad9084-rx-hpc', rx2_device_name='axi-ad9084b-rx-b', tx1_device_name='axi-ad9084-tx-hpc', tx2_device_name='axi-ad9084-tx-b')

Bases: rx_tx, context_manager, sync_start

AD9084 Mixed-Signal Front End (MxFE)

property adc_frequency

adc_frequency: ADC frequency in Hz

property api_version

api_version: API version

property chip_version

chip_version: Chip version information

property dac_frequency

dac_frequency: DAC frequency in Hz

property jesd204_device_status

jesd204_device_status: Device jesd204 link status information

property jesd204_device_status_check

jesd204_device_status_check: Device jesd204 link status check

Returns ‘True’ in case error conditions are detected, ‘False’ otherwise

property jesd204_fsm_ctrl

jesd204_fsm_ctrl: jesd204-fsm control

property jesd204_fsm_error

jesd204_fsm_error: jesd204-fsm error

property jesd204_fsm_paused

jesd204_fsm_paused: jesd204-fsm paused

property jesd204_fsm_resume

jesd204_fsm_resume: jesd204-fsm resume

property jesd204_fsm_state

jesd204_fsm_state: jesd204-fsm state

property loopback_mode

loopback_mode: Enable loopback mode RX->TX

When enabled JESD RX FIFO is connected to JESD TX FIFO, making the entire datasource for the TX path the RX path. No data is passed into the TX path from off-chip when 1. For this mode to function correctly the JESD configuration between RX and TX must be identical and only use a single link.

property path_map

path_map: Map of channelizers both coarse and fine to individual driver channel names

property rx_channel_nco_frequencies

rx_channel_nco_frequencies: Receive path fine DDC NCO frequencies

property rx_channel_nco_phases

rx_channel_nco_phases: Receive path fine DDC NCO phases

property rx_main_nco_frequencies

rx_main_nco_frequencies: Receive path coarse DDC NCO frequencies

property rx_main_nco_phases

rx_main_nco_phases: Receive path coarse DDC NCO phases

property rx_nyquist_zone

rx_nyquist_zone: ADC nyquist zone. Options are: odd, even

property rx_sample_rate

rx_sampling_frequency: Sample rate after decimation

property rx_test_mode

rx_test_mode: NCO Test Mode

property tx_channel_nco_frequencies

tx_channel_nco_frequencies: Transmit path fine DUC NCO frequencies

property tx_channel_nco_gain_scales

tx_channel_nco_gain_scales Transmit path fine DUC NCO gain scale

property tx_channel_nco_phases

tx_channel_nco_phases: Transmit path fine DUC NCO phases

property tx_channel_nco_test_tone_en

tx_channel_nco_test_tone_en: Transmit path fine DUC NCO test tone enable

property tx_channel_nco_test_tone_scales

tx_channel_nco_test_tone_scales: Transmit path fine DUC NCO test tone scale

property tx_ddr_offload

tx_ddr_offload: Enable DDR offload

When true the DMA will pass buffers into the BRAM FIFO for data repeating. This is necessary when operating at high DAC sample rates. This can reduce the maximum buffer size but data passed to DACs in cyclic mode will not underflow due to memory bottlenecks.

property tx_main_nco_frequencies

tx_main_nco_frequencies: Transmit path coarse DUC NCO frequencies

property tx_main_nco_phases

tx_main_nco_phases: Transmit path coarse DUC NCO phases

property tx_main_nco_test_tone_en

tx_main_nco_test_tone_en: Transmit path coarse DUC NCO test tone enable

property tx_main_nco_test_tone_scales

tx_main_nco_test_tone_scales: Transmit path coarse DUC NCO test tone scale

property tx_sample_rate

tx_sampling_frequency: Sample rate before interpolation