FPGA Features
Direct Digital Synthesizers
For FPGA based systems ADI reference designs include direct digital synthesizers (DDS) which can generate tones with arbitrary phase, frequency, and amplitude. For each individual DAC channel there are two DDSs which can have a unique phase, frequency, and phase. To configure the DDSs there are a number of methods and properties available depending on the complexity of the configuration.
For the most basic or easiest configuration options use the methods dds_single_tone and dds_dual_tone which generate a one tone or two tones respectively on a specific channel.
import adi
sdr = adi.ad9361()
# Generate a single complex tone
dds_freq_hz = 10000
dds_scale = 0.9
# Enable all DDSs
sdr.dds_single_tone(dds_freq_hz, dds_scale)
To configure DDSs individually a list of scales can be passed to the properties dds_scales, dds_frequencies, and dds_phases.
import adi
sdr = adi.ad9361()
n = len(sdr.dds_scales)
# Enable all DDSs
sdr.dds_enabled = [True] * n
# Set all DDSs to same frequency, scale, and phase
dds_freq_hz = 10000
sdr.dds_phases = [0] * n
sdr.dds_frequencies = [dds_freq_hz] * n
sdr.dds_scales = [0.9] * n
DDS Methods
- class adi.dds.dds
DDS Signal generators: Each reference design contains two DDSs per channel. this allows for two complex tones to be generated per complex channel.
- dds_dual_tone(frequency1, scale1, frequency2, scale2, channel=0)
Generate two tones simultaneously using the DDSs For complex data devices this will create two complex or single sided tones spectrally using four DDSs. For non-complex devices the tone will use two DDSs.
- parameters:
- frequency1: type=integer
Frequency of first tone in hertz of the generated tone. This must be less than 1/2 the sample rate.
- scale1: type=float
Scale of the first tone generated tone in range [0,1]. At 1 the tone will be full-scale.
- frequency2: type=integer
Frequency of second tone in hertz of the generated tone. This must be less than 1/2 the sample rate.
- scale2: type=float
Scale of the second tone generated tone in range [0,1]. At 1 the tone will be full-scale.
- channel: type=integer
Channel index to generate tone from. This is zero based and for complex devices this index relates to the pair of related converters. For non-complex devices this is the index of the individual converters.
- property dds_enabled
DDS generator enable state
- property dds_frequencies
Frequencies of DDSs in Hz
- property dds_phases
Phases of DDS signal generators. Range in millidegrees [0,360000]
- property dds_scales
Scale of DDS signal generators Ranges [0,1]
- dds_single_tone(frequency, scale, channel=0)
Generate a single tone using the DDSs For complex data devices this will create a complex or single sided tone spectrally using two DDSs. For non-complex devices the tone will use a single DDS.
- parameters:
- frequency: type=integer
Frequency in hertz of the generated tone. This must be less than 1/2 the sample rate.
- scale: type=float
Scale of the generated tone in range [0,1]. At 1 the tone will be full-scale.
- channel: type=integer
Channel index to generate tone from. This is zero based and for complex devices this index relates to the pair of related converters. For non-complex devices this is the index of the individual converters.
- disable_dds()
Disable all DDS channels and set all output sources to zero.
DMA Synchronization
In certain HDL reference designs it is possible to synchronize transfers between the transmit and receive data paths. This is useful for applications such as radar processing, communications, instrumentation, and general testing.
This works by leveraging special control signals inside the HDL design to trigger receive captures from transmitted buffers. These are controlled through the sync_start class, which provide explicit control over when data is transmitted or released from the DMA in the FPGA fabric. This transmit or trigger will in turn allow data into the receive DMA at this moment in time. The exact methods and their sequence are described in the flowchart below.
A full example that leverages this control is ad9081_sync_start_example.py.
Sync_Start Methods
- class adi.sync_start.sync_start
Synchronization Control: This class allows for synchronous transfers between transmit and receive data movement or captures.
- property rx_sync_start
rx_sync_start: Issue a synchronisation request
- Possible values are:
arm: Writing this key will arm the trigger mechanism sensitive to an external sync signal. Once the external sync signal goes high it synchronizes channels within a ADC, and across multiple instances. This bit has an effect only the EXT_SYNC synthesis parameter is set.
disarm: Writing this key will disarm the trigger mechanism sensitive to an external sync signal. This bit has an effect only the EXT_SYNC synthesis parameter is set.
trigger_manual: Writing this key will issue an external sync event if it is hooked up inside the fabric. This key has an effect only the EXT_SYNC synthesis parameter is set. This key self clears.
- property rx_sync_start_available
rx_sync_start_available: Returns a list of possible keys used for rx_sync_start
- property tx_sync_start
tx_sync_start: Issue a synchronisation request
- Possible values are:
arm: Writing this key will arm the trigger mechanism sensitive to an external sync signal. Once the external sync signal goes high it synchronizes channels within a DAC, and across multiple instances. This bit has an effect only the EXT_SYNC synthesis parameter is set.
disarm: Writing this key will disarm the trigger mechanism sensitive to an external sync signal. This bit has an effect only the EXT_SYNC synthesis parameter is set.
trigger_manual: Writing this key will issue an external sync event if it is hooked up inside the fabric. This key has an effect only the EXT_SYNC synthesis parameter is set. This key self clears.
- property tx_sync_start_available
tx_sync_start_available: Returns a list of possible keys used for tx_sync_start