AD469X-FMC HDL project#

Overview#

The AD469X HDL reference design provides all the interfaces that are necessary to interact with the devices on the EVAL-AD4696 board.

The design has a SPI Engine instance to control and acquire data from the AD4696 16-bit precisions ADC, providing support to capture continuous samples at maximum sampling rate. Currently the design supports the Zedboard.

Supported boards#

EVAL-AD4696

Supported devices#

Supported carriers#

ZedBoard on FMC slot

Block design#

The reference design uses the standard SPI Engine Framework to interface the AD4696 ADC in single SDO Mode. The SPI Engine Offload module, which can be used to capture continuous data stream at maximum data rate, is triggered by the BUSY signal of the device.

Block diagram#

The data path and clock domains are depicted in the below diagram:

CPU/Memory interconnects addresses#

The addresses are dependent on the architecture of the FPGA, having an offset added to the base address from HDL(see more at HDL Architecture).

Instance	Address
axi_ad469x_dma	0x44A3_0000
spi_clkgen	0x44A7_0000
spi_ad469x_axi_regmap	0x44A0_0000
ad469x_trigger_gen	0x44B0_0000

I2C connections#

I2C type	I2C manager instance	Alias	Address	I2C subordinate
PL	iic_fmc	axi_iic_fmc	0x4162_0000	—
PL	iic_main	axi_iic_main	0x4160_0000	—

SPI connections#

SPI type	SPI manager instance	SPI subordinate	CS
PL	axi_spi_engine	ad469x	0

GPIOs#

The Software GPIO number is calculated as follows:

Zynq-7000: if PS7 is used, then offset is 54

GPIO signal	Direction	HDL GPIO EMIO	Software GPIO
	(from FPGA view)		Zynq-7000
ad469x_resetn	INOUT	32	86

Interrupts#

Below are the Programmable Logic interrupts used in this project.

Instance name	HDL	Linux Zynq	Actual Zynq
axi_ad469x_dma	13	57	89
spi_ad469x	12	56	88

Building the HDL project#

The design is built upon ADI’s generic HDL reference design framework. ADI does not distribute the bit/elf files of these projects so they must be built from the sources available here. To get the source you must clone the HDL repository, and then build the project as follows:

Linux/Cygwin/WSL

user@analog:~$ cd hdl/projects/ad469x_fmc/zed
user@analog:~/hdl/projects/ad469x_fmc/zed$ make

A more comprehensive build guide can be found in the Build an HDL project user guide.

Resources#

HDL related#

AD469X_FMC HDL project source code

IP name	Source code link	Documentation link
AXI_CLKGEN	library/axi_dmac	[Wiki]
AXI_DMAC	library/axi_dmac	here
AXI_HDMI_TX	library/axi_hdmi_tx	[Wiki]
AXI_I2S_ADI	library/axi_i2s_adi	—
AXI_PWM_GEN	library/axi_pwm_gen	[Wiki]
AXI_SPDIF_TX	library/axi_spdif_tx	—
AXI_SPI_ENGINE	library/spi_engine/axi_spi_engine	here
AXI_SYSID	library/axi_sysid	[Wiki]
SPI_ENGINE_EXECUTION	library/spi_engine/spi_engine_execution	here
SPI_ENGINE_INTERCONNECT	library/spi_engine/spi_engine_interconnect	here
SPI_ENGINE_OFFLOAD	library/spi_engine/spi_engine_offload	here
SYSID_ROM	library/sysid_rom	[Wiki]
UTIL_I2C_MIXER	library/util_i2c_mixer	here

SPI Engine Framework documentation

More information#

ADI HDL User guide

Support#

Analog Devices, Inc. will provide limited online support for anyone using the reference design with ADI components via the EngineerZone FPGA reference designs forum.

For questions regarding the ADI Linux device drivers, device trees, etc. from our Linux GitHub repository, the team will offer support on the EngineerZone Linux software drivers forum.

For questions concerning the ADI No-OS drivers, from our No-OS GitHub repository, the team will offer support on the EngineerZone microcontroller No-OS drivers forum.

It should be noted, that the older the tools’ versions and release branches are, the lower the chances to receive support from ADI engineers.