AXI TDD#

The AXI Time-Division Duplexing Controller IP core is a pulse wave generator capable of addressing RF applications which require Time Division Duplexing, as well as controlling other modules of general applications through its dedicated 32 channel outputs.

The reason of creating the generic TDD controller was to reduce the naming confusion around the existing repurposed TDD core built for AD9361, as well as expanding its number of output channels for systems which require more than six controlling signals.

Note

TDD (Time-Division Duplex) mode allows the user to control the time period of the receive and transmit bursts.

Features#

Up to 32 independent output channels
Start/stop time values per channel
Enable and polarity bit values per channel
32 bit-max internal reference counter
Initial startup delay before wave generation
Configurable frame length and number of frames per burst
3 sources of synchronization: external, internal and software generated

Files#

Name	Description
library/axi_tdd/axi_tdd.sv	Top module.
library/axi_tdd/axi_tdd_pkg.sv	SystemVerilog Package.
library/axi_tdd/axi_tdd_regmap.sv	Register Map with CDC synchronizers.
library/axi_tdd/axi_tdd_counter.sv	Internal counters and FSM logic.
library/axi_tdd/axi_tdd_channel.sv	Channel waveform generator.
library/axi_tdd/axi_tdd_sync_gen.sv	Synchronization pulse generator.
library/axi_tdd/axi_tdd_ip.tcl	TCL script to generate the Vivado IP-integrator project.
library/axi_tdd/axi_tdd_hw.tcl	TCL script to generate the Quartus IP-integrator project.

Configuration Parameters#

Name	Description	Default Value	Choices/Range
`ID`	Instance identification number	`0`
`CHANNEL_COUNT`	Number of channels	`8`	From 1 to 32.
`DEFAULT_POLARITY`	Initial channel polarity	`'b00000000`
`REGISTER_WIDTH`	Internal counter and register width	`32`	From 8 to 32.
`BURST_COUNT_WIDTH`	Burst counter width	`32`	From 8 to 32.
`SYNC_INTERNAL`	Enable support for internal sync signal	`1`	From 0 to 1.
`SYNC_EXTERNAL`	Enable support for external sync signal	`0`	From 0 to 1.
`SYNC_EXTERNAL_CDC`	Enable synchronization of external sync signal	`0`	From 0 to 1.
`SYNC_COUNT_WIDTH`	Sync generator counter width	`64`	From 0 to 64.

Interface#

s_axi

AXI-Lite bus slave, memory mapped AXI-Lite bus that provides access to module’s register map.

Physical Port	Logical Port	Direction
`s_axi_awaddr`	`AWADDR`	in [9:0]
`s_axi_awprot`	`AWPROT`	in [2:0]
`s_axi_awvalid`	`AWVALID`	in
`s_axi_awready`	`AWREADY`	out
`s_axi_wdata`	`WDATA`	in [31:0]
`s_axi_wstrb`	`WSTRB`	in [3:0]
`s_axi_wvalid`	`WVALID`	in
`s_axi_wready`	`WREADY`	out
`s_axi_bresp`	`BRESP`	out [1:0]
`s_axi_bvalid`	`BVALID`	out
`s_axi_bready`	`BREADY`	in
`s_axi_araddr`	`ARADDR`	in [9:0]
`s_axi_arprot`	`ARPROT`	in [2:0]
`s_axi_arvalid`	`ARVALID`	in
`s_axi_arready`	`ARREADY`	out
`s_axi_rdata`	`RDATA`	out [31:0]
`s_axi_rresp`	`RRESP`	out [1:0]
`s_axi_rvalid`	`RVALID`	out
`s_axi_rready`	`RREADY`	in

s_axi_aclk

System clock.

Physical Port	Logical Port	Direction	Dependency
`s_axi_aclk`	`CLK`	in

s_axi_aresetn

System reset, synchronous active low reset.

Physical Port	Logical Port	Direction	Dependency
`s_axi_aresetn`	`RST`	in

clk

Core clock.

Physical Port	Logical Port	Direction	Dependency
`clk`	`CLK`	in

rst

Physical Port	Logical Port	Direction	Dependency
`rst`	`RST`

Ports

Physical Port	Direction	Description
`resetn`	in	Core reset, synchronous active low reset.
`sync_in`	in	External synchronization input signal.
`sync_out`	out	Module synchronization output signal.
`tdd_channel`	out [7:0]	Channels output.

Theory of Operation#

The central idea of the TDD controller is “frame”-based operation, i.e. all the timing defined for the individual channels is relative to the beginning of a frame. The FRAME_LENGTH value controls the length of a single frame, while the BURST_COUNT value controls how many frames should be played after enabling the device (a value of 0 means the frames will be repeated indefinitely). Before the start of a burst, an optional startup delay is inserted, defined by the STARTUP_DELAY value in clock cycles.

This diagram illustrates how different channels can be enabled at different times relative to the beginning of a frame.

Note

While the above graphic shows all channels being enabled in a stacked manner, they are completely independent of each other.

Detailed Description#

In order to begin its operation, the peripheral must be enabled. This is done by setting the ENABLE bit. Next, the peripheral waits to receive a synchronization signal. There are 3 possible sync sources, which can be independently activated through their corresponding enabling bits: SYNC_INT, SYNC_EXT and SYNC_SOFT can all be active at the same time.

The external synchronization capability allows the alignment of frames between multiple devices in different locations, for example using a GPSDO 1 PPS output. The internal sync signal is generated based on a dedicated counter, when its value matches the one defined in SYNC_PERIOD_LOW / SYNC_PERIOD_HIGH. The software generated sync pulse is triggered at an arbitrary point in time when writing a ‘1’ value in SYNC_SOFT.

The next diagram shows the peripheral’s FSM, which transitions between 4 states: IDLE, ARMED, WAITING and RUNNING.

In case a synchronization signal is received while the TDD core is running, the signal can reset the internal counter to zero by setting SYNC_RST to ‘1’. This can alter the counter value in both WAITING or RUNNING states.

The generic TDD controller can have up to 32 output channels, each of them having its unique values when the channel is set/reset under CHX_ON / CHX_OFF. They are continuously compared to the internal counter’s value while the core is RUNNING.

Every bit in CHANNEL_ENABLE / CHANNEL_POLARITY corresponds to a specific channel. The bit position is correlated to the channel index, so the LSB will always be associated with CH0 and the MSB with CH31.

The following registers will not be updated unless the peripheral is disabled:

BURST_COUNT
STARTUP_DELAY
FRAME_LENGTH
CHANNEL_POLARITY
SYNC_PERIOD_LOW
SYNC_PERIOD_HIGH
CHX_ON
CHX_OFF

The user must configure them before enabling the peripheral. Any subsequent write while the peripheral is enabled will be ignored.

An exception to this rule is CHANNEL_ENABLE, which allows enabling / disabling independent channels on-the-fly. The new value will come into effect when in ARMED state or at the end of a frame. CONTROL can also be modified on-the-fly with immediate effect (after going through the synchronization stage).

STATUS can be used for debugging purposes, reflecting the current peripheral state.

By adapting the synthesis parameters to the application requirements, the module is highly flexible and can substantially reduce resource utilization.

Register Map#

Generic TDD Control (axi_tdd) register map

DWORD	BYTE	Reg Name				Description
		BITS	Field Name	Type	Default Value	Description
`0x0`	`0x0`	`VERSION`				Version of the peripheral. Follows semantic versioning. Current version 2.00.62.
		`[31:16]`	`VERSION_MAJOR`	`RO`	`0x0002`
		`[15:8]`	`VERSION_MINOR`	`RO`	`0x00`
		`[7:0]`	`VERSION_PATCH`	`RO`	`0x62`
`0x1`	`0x4`	`PERIPHERAL_ID`
		`[31:0]`	`PERIPHERAL_ID`	`RO`	`ID`	Value of the ID configuration parameter.
`0x2`	`0x8`	`SCRATCH`
		`[31:0]`	`SCRATCH`	`RW`	`0x00000000`	Scratch register useful for debug.
`0x3`	`0xc`	`IDENTIFICATION`
		`[31:0]`	`IDENTIFICATION`	`RO`	`0x5444444e`	Peripheral identification (‘T’, ‘D’, ‘D’, ‘N’).
`0x4`	`0x10`	`INTERFACE_DESCRIPTION`
		`[30:24]`	`SYNC_COUNT_WIDTH`	`RO`	`SYNC_COUNT_WIDTH`	Width of internal synchronization counter.
		`[21:16]`	`BURST_COUNT_WIDTH`	`RO`	`BURST_COUNT_WIDTH`	Width of burst counter.
		`[13:8]`	`REGISTER_WIDTH`	`RO`	`REGISTER_WIDTH`	Width of internal reference counter and timing registers.
		`[7:7]`	`SYNC_EXTERNAL_CDC`	`RO`	`SYNC_EXTERNAL_CDC`	Enable CDC for external synchronization pulse.
		`[6:6]`	`SYNC_EXTERNAL`	`RO`	`SYNC_EXTERNAL`	Enable external synchronization support.
		`[5:5]`	`SYNC_INTERNAL`	`RO`	`SYNC_INTERNAL`	Enable internal synchronization support.
		`[4:0]`	`CHANNEL_COUNT_EXTRA`	`RO`	`CHANNEL_COUNT_EXTRA`	Number of channels starting from CH1, excluding CH0. `CHANNEL_COUNT_EXTRA = CHANNEL_COUNT-1`
`0x5`	`0x14`	`DEFAULT_POLARITY`
		`[31:0]`	`DEFAULT_POLARITY`	`RO`	`DEFAULT_POLARITY`	Default polarity per every channel - LSB corresponds to CH0, MSB to CH31.
`0x10`	`0x40`	`CONTROL`				TDD Control
		`[4:4]`	`SYNC_SOFT`	`RW1C`	`0x0`	Trigger the TDD core through a register write.
		`[3:3]`	`SYNC_EXT`	`RW`	`0x0`	Enable external sync trigger. This bit is implemented if `SYNC_EXTERNAL` is set.
		`[2:2]`	`SYNC_INT`	`RW`	`0x0`	Enable internal sync trigger. This bit is implemented if `SYNC_INTERNAL` is set.
		`[1:1]`	`SYNC_RST`	`RW`	`0x0`	Reset the internal counter while running when receiving a sync event.
		`[0:0]`	`ENABLE`	`RW`	`0x0`	Module enable.
`0x11`	`0x44`	`CHANNEL_ENABLE`				TDD Channel Enable
		`[31:0]`	`CHANNEL_ENABLE`	`RW`	`0x00000000`	Enable bits per channel - LSB corresponds to CH0, MSB to CH31.
`0x12`	`0x48`	`CHANNEL_POLARITY`				TDD Channel Polarity
		`[31:0]`	`CHANNEL_POLARITY`	`RW`	`0x00000000`	Polarity bits per channel - LSB corresponds to CH0, MSB to CH31.
`0x13`	`0x4c`	`BURST_COUNT`				TDD Number of frames per burst
		`[31:0]`	`BURST_COUNT`	`RW`	`0x00000000`	If set to 0 and enabled - the controller operates in TDD mode as long as the ENABLE bit is set. If set to a non-zero value, the controller operates for the set number of frames and then stops.
`0x14`	`0x50`	`STARTUP_DELAY`				TDD Transmission startup delay
		`[31:0]`	`STARTUP_DELAY`	`RW`	`0x00000000`	The initial delay value before the beginning of the first frame; defined in clock cycles-1.
`0x15`	`0x54`	`FRAME_LENGTH`				TDD Frame length
		`[31:0]`	`FRAME_LENGTH`	`RW`	`0x00000000`	The length of the transmission frame; defined in clock cycles-1.
`0x16`	`0x58`	`SYNC_PERIOD_LOW`				TDD Sync counter
		`[31:0]`	`SYNC_PERIOD_LOW`	`RW`	`0x00000000`	The LSB slice of the internal sync pulse period defined in clock cycles-1. This register is implemented if `SYNC_COUNT_WIDTH`>0.
`0x17`	`0x5c`	`SYNC_PERIOD_HIGH`				TDD Sync counter
		`[31:0]`	`SYNC_PERIOD_HIGH`	`RW`	`0x00000000`	The MSB slice of the internal sync pulse period defined in clock cycles-1. This register is implemented if `SYNC_COUNT_WIDTH`>32.
`0x18`	`0x60`	`STATUS`				Peripheral Status
		`[1:0]`	`STATE`	`RO`	`0x0`	The current state of the peripheral FSM; used for debugging purposes.
`0x20 + 0x2*n`	`0x80 + 0x8*n`	`CHn_ON`				Channel Set Where n is from 0 to 31.
		`[31:0]`	`CHn_ON`	`RW`	`0x00000000`	The offset (from frame count equal zero), when CHn is set.
`0x21 + 0x2*n`	`0x84 + 0x8*n`	`CHn_OFF`				Channel Reset Where n is from 0 to 31.
		`[31:0]`	`CHn_OFF`	`RW`	`0x00000000`	The offset (from frame count equal zero), when CHn is reset.

Access Type	Name	Description
RO	Read-only	Reads will return the current register value. Writes have no effect.
RW	Read-write	Reads will return the current register value. Writes will change the current register value.
RW1C	Read,write-1-to-clear	Reads will return the current register value. Writing the register will clear those bits of the register which were set to 1 in the value written. Bits are set by hardware.

References#

HDL IP core at library/axi_tdd
Generic Time-Division Duplexing Controller on wiki