AD4170_ASDZ HDL project

Overview

The HDL reference design for the AD4170-4 and AD4170-8 provides a high resolution, 24-Bit, DC to 50 kHz Input Bandwidth, Multichannel, Low Noise Precision Sigma-Delta ADC with PGA.

The data acquisition board incorporates the AD4170-4 or AD4170-8, a DC to 50 kHz input bandwidth, low noise, high speed, completely integrated analog front end for high precision measurement applications.

The AD4170-4/8 offers output data rates from 7.6 SPS up to 500 kSPS. The device contains a low noise, 24-bit Σ-Δ analog-to-digital converter (ADC), and can be configured to have 4 differential inputs or 8 single-ended or pseudodifferential inputs. The on-chip low noise gain stage ensures that signals of small amplitude can be interfaced directly to the AD4170-4/8.

This project has a SPI Engine instance to control and acquire data from the AD4170-4/8 24-bit precision ADC. This instance provides support for capturing continuous samples at the maximum sample rate.

Supported boards

  • EVAL-AD4170-ASDZ

Supported devices

Supported carriers

Block design

Block diagram

The data path and clock domains are depicted in the below diagram:

AD4170-ASDZ block diagram

CPU/Memory interconnects addresses

The addresses are dependent on the architecture of the FPGA, having an offset added to the base address from HDL (see more at CPU/Memory interconnects addresses).

Instance

Zynq*/DE10-Nano**

spi_ad4170_axi_regmap*

0x44A0_0000

axi_ad4170_dma*

0x44A3_0000

spi_clkgen*

0x44A7_0000

axi_dmac_0**

0x0002_0000

axi_spi_engine_0**

0x0003_0000

Legend

  • * instantiated only for Cora Z7S

  • ** instantiated only for DE10-Nano

I2C connections

I2C type

I2C manager instance

Alias

Address

I2C subordinate

PL*

iic_ard

axi_iic_ard

0x4160_0000

24AA32A

PS**

i2c1

sys_hps_i2c1

—

—

Legend

  • * instantiated only for Cora Z7S

  • ** instantiated only for DE10-Nano

SPI connections

SPI type

SPI manager instance

SPI subordinate

CS

PL

axi_spi_engine

ad4170

0

GPIOs

The Software GPIO number is calculated as follows:

  • Cora Z7S: the offset is 54

GPIO signal

Direction

HDL GPIO EMIO

Software GPIO

(from FPGA view)

Zynq-7000

dig_aux[1]

INOUT

33

87

dig_aux[0]

INOUT

32

86

  • DE10-Nano: the offset is 32

GPIO signal

Direction

HDL GPIO EMIO

Software GPIO

(from FPGA view)

DE10-Nano

dig_aux[1]

INPUT

33

1

dig_aux[0]

INPUT

32

0

Interrupts

Below are the Programmable Logic interrupts used in this project.

Instance name

HDL

Linux Zynq

Actual Zynq

axi_ad4170_dma

13

57

89

spi_ad4170

12

56

88

axi_iic_ard

11

55

87

Instance name

HDL

Linux DE10-Nano

Actual DE10-Nano

axi_spi_engine_0

5

45

77

axi_dmac_0

4

44

76

Building the HDL project

The design is built upon ADI’s generic HDL reference design framework. ADI distributes the bit/elf files of these projects as part of the ADI Kuiper Linux. If you want to build the sources, ADI makes them available on the HDL repository. To get the source you must clone the HDL repository, and then build the project as follows:

Linux/Cygwin/WSL

~$

cd hdl/projects/ad4170_asdz/coraz7s

~/hdl/projects/ad4170_asdz/coraz7s$

make

~$

cd hdl/projects/ad4170_asdz/de10nano

~/hdl/projects/ad4170_asdz/de10nano$

make

A more comprehensive build guide can be found in the Build an HDL project user guide.

Resources

More information

Support

Analog Devices, Inc. will provide limited online support for anyone using the reference design with ADI components via the EngineerZone FPGA reference designs forum.

For questions regarding the ADI Linux device drivers, device trees, etc. from our Linux GitHub repository, the team will offer support on the EngineerZone Linux software drivers forum.

For questions concerning the ADI No-OS drivers, from our No-OS GitHub repository, the team will offer support on the EngineerZone microcontroller No-OS drivers forum.

It should be noted, that the older the tools’ versions and release branches are, the lower the chances to receive support from ADI engineers.