Util WFIFO#
The Util WFIFO core is designed to downscale the clock rate of the RX data path. There are scenarios when the device clock (interface clock) is too high (above 200 MHz), making it a challenge to integrate any processing cores between the device core and CPACK/DMA, because of the small timing margins. By reducing the clock rate of the data path, the user can easily integrate any custom processing core into the design.
To define the correct configuration, the following questions need to be answered:
What is the clock rate of the device core’s data interface? (dout_clk)
What is the data rate of the device core’s data interface? (
dout_valid@dout_clk
)What is the targeted clock rate of the data path (din_clk), and how we can achieve it, respecting the main rule of thumb: input data rate must be equal to the output data rate?
If the device clock rate is equal to the device data rate, the only solution to downscale the clock rate is to increase the data width of the output ports of the FIFO. Currently the util_wfifo supports four data width ratios: 1:1/1:2/1:4/1:8.
Features#
Supports Altera and AMD Xilinx devices.
Downscale the ADC data path’s clock rate.
Supports multiple channels (max 8 channels)
Files#
Name |
Description |
---|---|
Verilog source for the peripheral. |
Configuration Parameters#
Name |
Description |
Default Value |
Choices/Range |
---|---|---|---|
NUM_OF_CHANNELS |
The number of channels of the device. |
4 |
|
DIN_DATA_WIDTH |
The bus width of the input data (DMA bus width). |
32 |
|
DOUT_DATA_WIDTH |
The bus width of the output data (device core’s data interface bus width). |
64 |
|
DIN_ADDRESS_WIDTH |
The address width of the internal memory of the FIFO. |
8 |
Interface#
Physical Port |
Logical Port |
Direction |
Dependency |
---|---|---|---|
din_clk |
CLK |
in |
Physical Port |
Logical Port |
Direction |
Dependency |
---|---|---|---|
din_rst |
RST |
in |
Physical Port |
Logical Port |
Direction |
Dependency |
---|---|---|---|
dout_clk |
CLK |
in |
Physical Port |
Logical Port |
Direction |
Dependency |
---|---|---|---|
dout_rstn |
RST |
in |
Physical Port |
Direction |
Dependency |
Description |
---|---|---|---|
din_ovf |
out |
Input data overflow. |
|
dout_ovf |
in |
Output data overflow. |
|
din_enable_* |
in |
Enable. |
|
din_valid_* |
in |
Valid. |
|
din_data_* |
in [31:0] |
Data. |
|
dout_enable_* |
out |
Enable. |
|
dout_valid_* |
out |
Valid. |
|
dout_data_* |
out [63:0] |
Data. |
References#
HDL IP core at library/util_wfifo