AXI Laser Driver#

The AXI Laser Driver IP core generates all the necessary control signals for the ad_fmclidar1_ebz prototyping platform, to drive the laser, switch between the TIA channels and synchronize all the data flow inside the FPGA. This documentation covers the main functionality of the IP core and its software programmable registers.

Features#

  • PWM generator with a free running counter

  • Software configurable frequency and pulse width for the PWM

  • Control and status lines for the ADP3624 MOSFET driver

  • Software configurable interrupts

  • Software configurable TIA channel sequencer

Files#

Name

Description

library/axi_laser_driver/axi_laser_driver.v

Verilog source for the peripheral.

Configuration Parameters#

Name

Description

Default Value

Choices/Range

ID

Core ID should be unique for each instance of the IP

0

ASYNC_CLK_EN

Bit must be set if the core clock is different from the AXI Memory Mapped interface clock

True

PULSE_WIDTH

The pulse width of the generated signal. The resolution is the core clock’s time period.

7

From 0 to 2147483647.

PULSE_PERIOD

The period of the generated signal. The resolution is the core clock’s time period.

10

From 0 to 2147483647.

Interface#

Physical Port

Logical Port

Direction

Dependency

s_axi_awaddr AWADDR

in [15:0]

s_axi_awprot AWPROT

in [2:0]

s_axi_awvalid AWVALID

in

s_axi_awready AWREADY

out

s_axi_wdata WDATA

in [31:0]

s_axi_wstrb WSTRB

in [3:0]

s_axi_wvalid WVALID

in

s_axi_wready WREADY

out

s_axi_bresp BRESP

out [1:0]

s_axi_bvalid BVALID

out

s_axi_bready BREADY

in

s_axi_araddr ARADDR

in [15:0]

s_axi_arprot ARPROT

in [2:0]

s_axi_arvalid ARVALID

in

s_axi_arready ARREADY

out

s_axi_rdata RDATA

out [31:0]

s_axi_rresp RRESP

out [1:0]

s_axi_rvalid RVALID

out

s_axi_rready RREADY

in

Physical Port

Logical Port

Direction

Dependency

s_axi_aclk CLK

in

Physical Port

Logical Port

Direction

Dependency

s_axi_aresetn RST

in

Physical Port

Logical Port

Direction

Dependency

ext_clk CLK

in

ASYNC_CLK_EN = 1

Physical Port

Direction

Dependency

Description

driver_en_n

out

This line will control the MOSFET driver’s shot down pin. If set the MOSFET driver is not working.

driver_pulse

out

Generated pulse, which is used to drive the laser

driver_otw_n

in

Over temperature warning flag of the MOSFET driver.

driver_dp_reset

out

A reset signal, which asserts right before the generated pulse. This signal can be used for preconditioning various IPs of the data path.

tia_chsel

out [7:0]

Control lines for the TIA channel multiplexer.

irq

out

Interrupt signal.

Register Map#

DWORD

BYTE

Reg Name

Description

BITS

Field Name

Type

Default Value

Description

0x0 0x0 VERSION

Version of the peripheral. Follows semantic versioning. Current version 1.00.61.

[31:16] VERSION_MAJOR RO 0x0001

[15:8] VERSION_MINOR RO 0x01

[7:0] VERSION_PATCH RO 0x61

0x1 0x4 ID

[31:0] ID RO

‘’ID’’

Value of the ID configuration parameter. In case of multiple instances, each instance will have a unique ID.

0x2 0x8 SCRATCH

[31:0] SCRATCH RW 0x00000000

Scratch register useful for debug.

0x4 0x10 CONFIG_PWM

Configuration Registers

[0:0] RESET RW 0x1

Reset bit of the core. By default the core is in reset.

0x5 0x14 CONFIG_PERIOD

Configuration Registers

[31:0] PWM_PERIOD RW

‘’PULSE_​PERIOD’’

The period of the generated signal. The resolution is the core clock’s time period. LOAD_CONFIG bit must be asserted to load the registers value into the PWM logic.

0x6 0x18 CONFIG_WIDTH

Configuration Registers

[31:0] PWM_WIDTH RW

‘’PULSE_​WIDTH’’

The pulse width of the generated signal. The resolution is the core clock’s time period. LOAD_CONFIG bit must be asserted to load the registers value into the PWM logic.

0x21 0x84 STATUS_LDRIVER

Configuration Registers

[0:0] DRIVER_OTW RO 0x0

The status of the OTW (over temperature warning flag) pin of the MOSFET driver.

0x22 0x88 EXT_CLK_MONITOR

Status Registers

[31:0] EXT_CLK_FREQ RO 0x00000000

The core clock’s frequency. This clock is used for example by PWM counter too. The number is represented as unsigned 16.16 format. Assuming a 100MHz processor clock the minimum is 1.523kHz and maximum is 6.554THz.

0x29 0xa4 IRQ_PENDING

Interrupt Registers

[0:0] IRQ_PULSE_PENDING RW1C 0x0

This bit is set if a pulse was generated, and the IRQ_PULSE_MASK bit is not set. Set this bit after the interrupt was handled as required.

[1:1] IRQ_OTW_ENTER_PENDING RW1C 0x0

This bit is set if the MOSFET driver enters in OTW state, and the IRQ_OTW_ENTER_MASK bit is not set. Set this bit after the interrupt was handled as required.

[2:2] IRQ_OTW_EXIT_PENDING RW1C 0x0

This bit is set if the MOSFET driver enters in OTW state, and the IRQ_OTW_EXIT_MASK bit is not set. Set this bit after the interrupt was handled as required.

0x2a 0xa8 IRQ_SOURCE

Interrupt Registers

[0:0] IRQ_PULSE_SOURCE RO 0x0

This bit is set if a pulse was generated. Cleared together with the corresponding IRQ_PENDING bit.

[1:1] IRQ_OTW_ENTER_SOURCE RO 0x0

This bit is set if the MOSFET driver enters in OTW state. Cleared together with the corresponding IRQ_PENDING bit.

[2:2] IRQ_OTW_EXIT_SOURCE RO 0x0

This bit is set if the MOSFET driver exits in OTW state. Cleared together with the corresponding IRQ_PENDING bit.

0x2b 0xac SEQUENCER_CONTROL

TIA Sequencer Registers

[0:0] SEQUENCER_ENABLE RW 0x0

Set this bit to enable the TIA channel sequencer.

[1:1] AUTO_SEQUENCE_EN RW 0x1

If set, the sequencer runs in auto mode, using the predefined sequence. Otherwise the software must set the TIA_MANUAL_CONFIG register to change the TIA channel selection.

0x2c 0xb0 SEQUENCER_OFFSET

TIA Sequencer Registers

[31:0] TIA_CHSEL_OFFSET RW 0x00000000

Defines the time between setting the TIA channel select lines and the next generated pulse.

0x2d 0xb4 SEQUENCE_AUTO_CONFIG

TIA Sequencer Registers

[1:0] SEQUENCE_VALUE0 RW 0x0

The value of the TIA channel selects lines in the first sequence.

[5:4] SEQUENCE_VALUE1 RW 0x1

The value of the TIA channel selects lines in the second sequence.

[9:8] SEQUENCE_VALUE2 RW 0x2

The value of the TIA channel selects lines in the third sequence.

[13:12] SEQUENCE_VALUE3 RW 0x3

The value of the TIA channel selects lines in the fourth sequence.

0x2e 0xb8 TIA_MANUAL_CONFIG

TIA Sequencer Registers

[1:0] TIA0_CHSEL_MANUAL RW 0x0

The value of the TIA0 channel selects lines in manual mode.

[5:4] TIA1_CHSEL_MANUAL RW 0x0

The value of the TIA0 channel selects lines in manual mode.

[9:8] TIA2_CHSEL_MANUAL RW 0x0

The value of the TIA0 channel selects lines in manual mode.

[13:12] TIA3_CHSEL_MANUAL RW 0x0

The value of the TIA0 channel selects lines in manual mode

Access Type

Name

Description

RO

Read-only

Reads will return the current register value. Writes have no effect.

RW

Read-write

Reads will return the current register value. Writes will change the current register value.

RW1C

Read,write-1-to-clear

Reads will return the current register value. Writing the register will clear those bits of the register which were set to 1 in the value written. Bits are set by hardware.