AXI Logic Analyzer#

The AXI Logic Analyzer IP core implements both a logic analyzer and a pattern generator, sharing the same pins. More about the generic framework interfacing ADCs can be read here at Generic AXI ADC. and for DACs at Generic AXI DAC.

Features#

AXI Lite control/status interface
16-channel digital I/O pins
Supports open drain outputs, configurable per pin
Down-sampling
Up-sampling
Digital triggering
Control history variable FIFO

Files#

Name	Description
library/axi_logic_analyzer/axi_logic_analyzer.v	Verilog source for the peripheral.

Block Diagram#

Interface#

s_axi

Standard AXI Slave Memory Map interface.

Physical Port	Logical Port	Direction
`s_axi_awaddr`	`AWADDR`	in [6:0]
`s_axi_awprot`	`AWPROT`	in [2:0]
`s_axi_awvalid`	`AWVALID`	in
`s_axi_awready`	`AWREADY`	out
`s_axi_wdata`	`WDATA`	in [31:0]
`s_axi_wstrb`	`WSTRB`	in [3:0]
`s_axi_wvalid`	`WVALID`	in
`s_axi_wready`	`WREADY`	out
`s_axi_bresp`	`BRESP`	out [1:0]
`s_axi_bvalid`	`BVALID`	out
`s_axi_bready`	`BREADY`	in
`s_axi_araddr`	`ARADDR`	in [6:0]
`s_axi_arprot`	`ARPROT`	in [2:0]
`s_axi_arvalid`	`ARVALID`	in
`s_axi_arready`	`ARREADY`	out
`s_axi_rdata`	`RDATA`	out [31:0]
`s_axi_rresp`	`RRESP`	out [1:0]
`s_axi_rvalid`	`RVALID`	out
`s_axi_rready`	`RREADY`	in

s_axi_aclk

Physical Port	Logical Port	Direction	Dependency
`s_axi_aclk`	`CLK`	in

s_axi_aresetn

Physical Port	Logical Port	Direction	Dependency
`s_axi_aresetn`	`RST`	in

clk

Main clock.

Physical Port	Logical Port	Direction	Dependency
`clk`	`CLK`	in

clk_out

Clock on which the logic analyzer/pattern generator related modules are running. It is a selection between clk and data[0].

Physical Port	Logical Port	Direction	Dependency
`clk_out`	`CLK`	out

Ports

Physical Port	Direction	Description
`data_i`	in [15:0]	Data input, used when working as logic analyzer.
`data_o`	out [15:0]	Data output, used when working as pattern generator.
`data_t`	out [15:0]	Data selection, switch between logic analyzer and pattern generator.
`trigger_i`	in [1:0]	Trigger pins, controlled by another IP.
`adc_valid`	out	Valid for the logic analyzer path.
`adc_data`	out [15:0]	Data for the logic analyzer path.
`dac_data`	in [15:0]	Data for the pattern generator path.
`dac_valid`	in	Valid for the pattern generator path.
`dac_read`	out	Read for the pattern generator path.
`external_rate`	in [2:0]	Information regarding the decimation rate used by the ADC decimation filters.
`external_valid`	in	Valid generated by ADC decimation path.
`external_decimation_en`	in	External decimation enabled.
`trigger_in`	in
`trigger_out`	out	Triggers data acquisition on the logic analyzer DMAC.
`trigger_out_adc`	out
`fifo_depth`	out [31:0]	Controls the depth of the variable FIFO, used for the trigger history on the logic analyzer path.

Detailed Description#

The AXI_LOGIC_ANALYZER IP implements both a logic analyzer and a pattern generator functionality.

There are 16-channel digital I/O pins. All the pins can be configured either as inputs (logic analyzer) or outputs (pattern generator). The pattern generator supports open drain outputs, configurable per pin.

The logic analyzer path can work at lower than the maximum rate by configuring the down sampling block. The same thing is done for the pattern generator using the up sampling block.

The logic analyzer, can be synchronized (data delayed) to the ADC path.

Triggering for the logic analyzer is implemented in this IP also. It can generate triggers based on external trigger signals, ADC (Oscilloscope) trigger and the 16-bit input signals. To order to provide data before triggering, a variable length FIFO should be used with this IP. The length of the FIFO is configured through the TRIGGER_DELAY register. It can be bypassed if TRIGGER_DELAY is 0.

For each of the 18 pins, triggering can be done based on rise edge, fall edge, any edge, high or low.

Register Map#

Logic Analyzer and Pattern Generator (axi_logic_analyzer) register map

DWORD	BYTE	Reg Name				Description
		BITS	Field Name	Type	Default Value	Description
`0x0`	`0x0`	`VERSION`				Version of the peripheral. Follows semantic versioning. Current version 2.1.0.
		`[31:16]`	`VERSION_MAJOR`	`RO`	`0x0002`
		`[15:8]`	`VERSION_MINOR`	`RO`	`0x01`
		`[7:0]`	`VERSION_PATCH`	`RO`	`0x00`
`0x1`	`0x4`	`SCRATCH`				Scratch Register
		`[31:0]`	`SCRATCH`	`RW`		Scratch register useful for debug.
`0x2`	`0x8`	`DIVIDER_COUNTER_LA`				Downsampling Counter
		`[31:0]`	`DIVIDER_COUNTER`	`RW`		Register used for down sampling the logic analyzer data. Sample data every (divider_counter + 1) samples
`0x3`	`0xc`	`DIVIDER_COUNTER_PG`				Upsampling Counter
		`[31:0]`	`DIVIDER_COUNTER`	`RW`		Register used for upsampling pattern generator data. Sample data every (divider counter + 1) samples
`0x4`	`0x10`	`IO_SELECTION`				Data Pins Direction
		`[15:0]`	`DIRECTION`	`RW`		Selects which pins are inputs(1) and which are outputs (0). Each bit configures the corresponding pin
`0x5`	`0x14`	`EDGE_DETECT_CONTROL`				Any Edge Triggering
		`[17:16]`	`TRIGGER`	`RW`		Enables any edge detection triggering based on the trigger pins
		`[15:0]`	`DATA`	`RW`		Enables any edge detection triggering based on the data pins
`0x6`	`0x18`	`RISE_EDGE_CONTROL`				Rise Edge Triggering
		`[17:16]`	`TRIGGER`	`RW`		Enables rise edge detection triggering based on the trigger pins
		`[15:0]`	`DATA`	`RW`		Enables rise edge detection triggering based on the data pins
`0x7`	`0x1c`	`FALL_EDGE_CONTROL`				Fall Edge Triggering
		`[17:16]`	`TRIGGER`	`RW`		Enables fall edge detection triggering based on the trigger pins
		`[15:0]`	`DATA`	`RW`		Enables fall edge detection triggering based on the data pins
`0x8`	`0x20`	`LOW_LEVEL_CONTROL`				Low Level Triggering
		`[17:16]`	`TRIGGER`	`RW`		Enables low level triggering based on the trigger pins
		`[15:0]`	`DATA`	`RW`		Enables low level triggering based on the data pins
`0x9`	`0x24`	`HIGH_LEVEL_CONTROL`				High Level Triggering
		`[17:16]`	`TRIGGER`	`RW`		Enables high level triggering based on the trigger pins
		`[15:0]`	`DATA`	`RW`		Enables high level triggering based on the data pins
`0xa`	`0x28`	`FIFO_DEPTH`				Controls the Dynamic Depth of the History FIFO
		`[31:0]`	`FIFO_DEPTH`	`RW`		Controls the depth of the history FIFO. Should be less than the maximum FIFO depth. If set to 0, the FIFO is bypassed and reset
`0xb`	`0x2c`	`TRIGGER_LOGIC`				Trigger Mix
		`[6:4]`	`TRIGGER_MUX_OUT`	`RW`		Final Trigger Selection Multiplexer Selects triggers: 0: TRIGGER_LOGIC 1: TRIGGER_ADC 2: TRIGGER_LOGIC AND TRIGGER_ADC 3: TRIGGER_LOGIC OR TRIGGER_ADC 4: TRIGGER_LOGIC XOR TRIGGER_ADC 7: TRIGGER DISABLED
		`[0:0]`	`TRIGGER_LOGIC`	`RW`		Combines the enable triggers through an OR (0) or an AND (1) gate
`0xc`	`0x30`	`CLOCK_SELECT`				Clock Selection Multiplexer
		`[0:0]`	`CLOCK_SELECT`	`RW`		Selects between clk(0) and data[0] (1) as clock for the logic analyzer and pattern generator paths
`0xd`	`0x34`	`OVERWRITE_MASK`				Overwrite data_o Value
		`[15:0]`	`OVERWRITE_MASK`	`RW`		If set to 1, the specific data_o pin will be driven by the value written in the OVERWRITE_DATA register, instead of the DMA
`0xe`	`0x38`	`OVERWRITE_DATA`				Overwrite Value for data_o
		`[15:0]`	`OVERWRITE_DATA`	`RW`		Overwrite value to drive data_o directly, when the mask is applied
`0xf`	`0x3c`	`INPUT_DATA`				Read the Value on data_i Bus
		`[15:0]`	`INPUT_DATA`	`RO`		The value of the input data, synchronized
`0x10`	`0x40`	`OUTPUT_MODE`				Controls Output Type
		`[0:0]`	`OUTPUT_MODE`	`RW`		Data output is in push-pull (0) or open-drain(1) mode
`0x11`	`0x44`	`TRIGGER_DELAY`				Control the Trigger Delay
		`[31:0]`	`TRIGGER_DELAY`	`RW`		Delays the start of data capture with TRIGGER_DELAY number of samples after the trigger
`0x12`	`0x48`	`TRIGGERED`				Indicates Triggering Status
		`[0:0]`	`TRIGGERED`	`RW1C`		Indicates if the trigger has been triggered since the last time this register has been reset.
`0x13`	`0x4c`	`STREAMING`				Controls Streaming Mode
		`[0:0]`	`STREAMING`	`RW`		If the streaming bit is set, after the trigger condition is met data will be continuosly captured by the DMA. The streaming bit must be set to 0 to reset triggering.
`0x14`	`0x50`	`TRIGGER_HOLDOFF`				Controls the Trigger hold off time
		`[31:0]`	`TRIGGER_HOLDOFF`	`RW`		Defines the time interval, after a trigger event, where the next trigger events will be ignored, until the end of the interval. The time interval is set by counter. Down-counting on the ADC clock(100MHz)/or external clock, if configured. The value written in the register is loaded in the counter at a trigger event
`0x15`	`0x54`	`PG_TRIGGER_CONFIG`				Pattern generator trigger configuration
		`[19:19]`	`EN_TRIGGER_LA`	`RW`		Enable trigger from Logic Analyzer
		`[18:18]`	`EN_TRIGGER_ADC`	`RW`		Enable trigger from ADC
		`[17:17]`	`EN_TRIGGER_TO`	`RW`		Enable trigger from To
		`[16:16]`	`EN_TRIGGER_TI`	`RW`		Enable trigger from Ti
		`[9:8]`	`HIGH_LEVEL`	`RW`		High level triggering for TRIGGER[0](Ti) or TRIGGER[1](To) pin
		`[7:6]`	`LOW_LEVEL`	`RW`		Low level triggering for TRIGGER[0](Ti) or TRIGGER[1](To) pin
		`[5:4]`	`FALL_EDGE`	`RW`		Falling edge triggering for TRIGGER[0](Ti) or TRIGGER[1](To) pin
		`[3:2]`	`RISE_EDGE`	`RW`		Rising edge triggering for TRIGGER[0](Ti) or TRIGGER[1](To) pin
		`[1:0]`	`ANY_EDGE`	`RW`		Any edge triggering for TRIGGER[0](Ti) or TRIGGER[1](To) pin
`0x14`	`0x50`	`DATA_DELAY_CONTROL`				Controls the synchronization to ADC data
		`[9:9]`	`MASTER_DELAY_CTRL`	`RW`		Select if the number of delay taps is chosen by the user(=1) or automatically(=0). Default is 0 or automatically
		`[8:8]`	`RATE_GEN_SELECT`	`RW`		Selects if the rate is generated by the logic analyzer(0) or it comes from the ADC(1). Default is 0 or logic analyzer
		`[5:0]`	`MANUAL_DATA_DELAY`	`RW`		If MASTER_DELAY_CTRL is set to user delay, the data will be delayed with a number of samples specified it the MANUAL_DATA_DELAY field

Access Type	Name	Description
RO	Read-only	Reads will return the current register value. Writes have no effect.
RW	Read-write	Reads will return the current register value. Writes will change the current register value.
RW1C	Read,write-1-to-clear	Reads will return the current register value. Writing the register will clear those bits of the register which were set to 1 in the value written. Bits are set by hardware.

References#

HDL IP core at library/axi_logic_analyzer
AXI LOGIC ANALYZER on wiki
7 Series IO
7 Series Clocking
7 Series libraries