AD9081/AD9082/AD9986/AD9988 HDL project

Overview

The AD9081-FMCA-EBZ / AD9082-FMCA-EBZ reference design (also known as Single MxFE) is a processor based (e.g. Microblaze) embedded system. This reference design works with EVAL-AD9986 and EVAL-AD9988 as well. The design consists from a receive and a transmit chain.

The receive chain transports the captured samples from ADC to the system memory (DDR). Before transferring the data to DDR the samples are stored in a buffer implemented on block rams from the FPGA fabric (util_adcfifo). The space allocated in the buffer for each channel depends on the number of currently active channels. It goes up to M x 64k samples if a single channel is selected or 64k samples per channel if all channels are selected.

The transmit chain transports samples from the system memory to the DAC devices. Before streaming out the data to the DAC through the JESD link the samples first are loaded into a buffer (util_dacfifo) which will cyclically stream the samples at the tx_device_clk data rate. The space allocated in the transmit buffer for each channel depends on the number of currently active channels. It goes up to M x 64k samples if a single channel is selected or 64k samples per channel if all channels are selected.

All cores from the receive and transmit chains are programmable through an AXI-Lite interface.

The transmit and receive chains can operate at different data rates having separate rx_device_clk/tx_device_clk and corresponding lane rates but must share the same reference clock.

Supported boards

Supported devices

Supported carriers

Note

EVAL-AD9988 can be an alternative to AD9081-FMCA-EBZ and EVAL-AD9986 can be an alternative to AD9082-FMCA-EBZ.

Both AD9081 and AD9988 have MxFE Quad, 16-bit, 12 GSPS RF DAC & Quad, 12-bit, 4 GSPS RF ADC,

The same goes for AD9082 and AD9986, both have MxFE Quad, 16-bit, 12 GSPS RF DAC & Dual, 12-bit, 6 GSPS RF ADC.

Evaluation board

Carrier

FMC slot

AD9081-FMCA-EBZ

A10SoC

FMCA

FM87

FMCA

VCK190

FMC0

VPK180

FMCP1

VCU118

FMC+

VCU128

FMC+

ZCU102

FMC HPC0

ZC706

FMC HPC

Evaluation board

Carrier

FMC slot

AD9082-FMCA-EBZ

VCK190

FMC0

VPK180

FMCP1

VCU118

FMC+

ZCU102

FMC HPC0

ZC706

FMC HPC

Warning

When using A10SoC in your setup, the following reworks are required on the evaluation board:

  • To avoid using an external clock source and fully rely on the HMC7044 clock chip, rotate the C6D/C4D caps in C5D/C3D position (Please note: In the latest version of the board, this is now the default configuration, so this configuration step might not be needed anymore).

  • If LEDS V1P0_LED and VINT_LED are not on, please depopulate R22M and populate R2M

For the carrier, A10SoC, the following reworks are mandatory: [Wiki] FMC Pin Connection Configuration

Warning

For FM87 setups, the following reworks are required on the evaluation board:

  • C39B, C40B: 50 ohm

For the carrier FM87, the following reworks are required:

  • R1433, R1434: 50 ohm

  • R1777, R1778: 50 ohm

  • C2488, C4289: 0 ohm

  • R1231, R1234: 1k ohm

  • R1230, R1233: 1k ohm

This project requires Quartus Pro 24.1!

Block design

Block diagram

The data path and clock domains are depicted in the below diagrams:

Configuration modes

The block design supports configuration of parameters and scales.

We have listed a couple of examples at section Building the HDL project and the default modes for each project.

Note

The parameters for Rx or Tx links can be changed from the system_project.tcl file, located in hdl/projects/ad9081_fmca_ebz/$CARRIER/system_project.tcl

Warning

Lane Rate = I/Q Sample Rate x M x N' x (10 \ 8) \ L

The following are the parameters of this project that can be configured:

  • JESD_MODE: used link layer encoder mode

    • 64B66B - 64b66b link layer defined in JESD204C, uses AMD IP as Physical Layer

    • 8B10B - 8b10b link layer defined in JESD204B, uses ADI IP as Physical Layer

  • RX_LANE_RATE: lane rate of the Rx link (MxFE to FPGA)

  • TX_LANE_RATE: lane rate of the Tx link (FPGA to MxFE)

  • REF_CLK_RATE: the rate of the reference clock

  • DEVICE_CLK_RATE: the rate of the device clock (Intel only)

  • [RX/TX]_JESD_M: number of converters per link

  • [RX/TX]_JESD_L: number of lanes per link

  • [RX/TX]_JESD_S: number of samples per frame

  • [RX/TX]_JESD_NP: number of bits per sample

  • [RX/TX]_NUM_LINKS: number of links

  • [RX/TX]_TPL_WIDTH

  • TDD_SUPPORT: set to 1, adds the TDD; enables external synchronization through TDD. Must be set to 1 when SHARED_DEVCLK=1

  • SHARED_DEVCLK

  • TDD_CHANNEL_CNT

  • TDD_SYNC_WIDTH

  • TDD_SYNC_INT

  • TDD_SYNC_EXT

  • TDD_SYNC_EXT_CDC: if enabled, the CDC circuitry for the external sync signal is added

  • [RX/TX]_KS_PER_CHANNEL: Number of samples stored in internal buffers in kilosamples per converter (M)

  • [ADC/DAC]_DO_MEM_TYPE

  • Check out this guide on more details regarding these parameters: AXI TDD

Clock scheme

The clock sources depend on the carrier that is used:

ZCU102

AD9081-FMCA-EBZ ZCU102 clock scheme

VCU118

AD9081-FMCA-EBZ VCU118 clock scheme

Limitations

Warning

For the parameter selection, the following restrictions apply:

CPU/Memory interconnects addresses

The addresses are dependent on the architecture of the FPGA, having an offset added to the base address from HDL (see more at CPU/Memory interconnects addresses).

Depending on the values of parameters $INTF_CFG, $ADI_PHY_SEL and $TDD_SUPPORT, some IPs are instatiated and some are not.

Check-out the table below to find out the conditions.

Instance

Depends on parameter

Zynq/Microblaze

ZynqMP

Versal

axi_mxfe_rx_xcvr

$INTF_CFG!=”TX” & $ADI_PHY_SEL==1

0x44A6_0000

0x84A6_0000

0xA4A6_00000

rx_mxfe_tpl_core

$INTF_CFG!=”TX”

0x44A1_0000

0x84A1_0000

0xA4A1_00000

axi_mxfe_rx_jesd

$INTF_CFG!=”TX”

0x44A9_0000

0x84A9_0000

0xA4A9_00000

axi_mxfe_rx_dma

$INTF_CFG!=”TX”

0x7C42_0000

0x9C42_0000

0xBC42_00000

mxfe_rx_data_offload

$INTF_CFG!=”TX”

0x7C45_0000

0x9C45_0000

0xBC45_00000

axi_mxfe_tx_xcvr

$INTF_CFG!=”RX” & $ADI_PHY_SEL==1

0x44B6_0000

0x84B6_0000

0xA4B6_00000

tx_mxfe_tpl_core

$INTF_CFG!=”RX”

0x44B1_0000

0x84B1_0000

0xA4B1_00000

axi_mxfe_tx_jesd

$INTF_CFG!=”RX”

0x44B9_0000

0x84B9_0000

0xA4B9_00000

axi_mxfe_tx_dma

$INTF_CFG!=”RX”

0x7C43_0000

0x9C43_0000

0xBC43_00000

mxfe_tx_data_offload

$INTF_CFG!=”RX”

0x7C44_0000

0x9C44_0000

0xBC44_00000

axi_tdd_0

$TDD_SUPPORT==1

0x7C46_0000

0x9C46_0000

0xBC46_00000

For the Intel carriers, only a part of the CPU interrupts are specified, as the rest depend on the values of $TX_NUM_OF_LANES and $TRANSCEIVER_TYPE (see projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_qsys.tcl for more details).

Instance

Intel

mxfe_rx_jesd204.link_reconfig

0x000C_0000

mxfe_rx_jesd204.link_management

0x000C_4000

mxfe_tx_jesd204.link_reconfig

0x000C_8000

mxfe_tx_jesd204.link_management

0x000C_C000

mxfe_rx_tpl.s_axi

0x000D_2000

mxfe_tx_tpl.s_axi

0x000D_4000

mxfe_rx_dma.s_axi

0x000D_8000

mxfe_tx_dma.s_axi

0x000D_C000

mxfe_gpio.s1

0x000E_0000

SPI connections

SPI type

SPI manager instance

SPI subordinate

CS

PS

spi0

AD9081

0

PS

spi1

HMC7044

0

GPIOs

GPIO signal

Direction

HDL GPIO EMIO

Software GPIO

Software GPIO

(from FPGA view)

Zynq-7000

Zynq MP

txen[1:0]

OUT

59:58

113:112

137:136

rxen[1:0]

OUT

57:56

111:110

135:134

rstb

OUT

55

109

133

hmc_sync

OUT

54

108

132

irqb[1:0]

IN

53:52

107:106

131:130

agc3[1:0]

IN

51:50

105:104

129:128

agc2[1:0]

IN

49:48

103:102

127:126

agc1[1:0]

IN

47:46

101:100

125:124

agc0[1:0]

IN

45:44

99:98

123:122

hmc_gpio1

INOUT

43

97

121

gpio[10:0]

INOUT

42:32

96:86

120:110

Interrupts

Below are the Programmable Logic interrupts used in this project.

Instance name

HDL

Linux Zynq

Actual Zynq

Linux ZynqMP

Actual ZynqMP

axi_mxfe_rx_dma

13

57

89

109

141

axi_mxfe_tx_dma

12

56

88

108

140

axi_mxfe_rx_jesd

11

55

87

107

139

axi_mxfe_tx_jesd

10

54

86

106

138

Building the HDL project

The design is built upon ADI’s generic HDL reference design framework. ADI distributes the bit/elf files of these projects as part of the ADI Kuiper Linux. If you want to build the sources, ADI makes them available on the HDL repository. To get the source you must clone the HDL repository.

Then go to the projects/ad9081_fmca_ebz or (projects/ad9082_fmca_ebz) location and run the make command by typing in you command prompt:

Example for building the project with parameters:

Linux/Cygwin/WSL

~$

cd hdl/projects/ad9081_fmca_ebz/zcu102

~/hdl/projects/ad9081_fmca_ebz/zcu102$

make RX_LANE_RATE=2.5 TX_LANE_RATE=2.5     \
     RX_JESD_L=8 RX_JESD_M=4 RX_JESD_S=1   \
     RX_JESD_NP=16 TX_JESD_L=8 TX_JESD_M=4 \
     TX_JESD_S=1 TX_JESD_NP=16

The following dropdowns contain tables with the parameters that can be used to configure this project, depending on the carrier used. Where a cell contains a — (dash) it means that the parameter doesn’t exist for that project (ad9081_fmca_ebz/$carrier or ad9082_fmca_ebz/$carrier).

Warning

For the parameter selection, the following restrictions apply:

NP notation is equivalent with N'

Parameter

Default value of the parameters depending on carrier

A10SoC

FM87

VCK190

VPK180

VCU118

VCU128

ZC706

ZCU102

JESD_MODE

—

64B66B

64B66B

64B66B

8B10B

8B10B

8B10B

8B10B

RX_LANE_RATE

10

15

24.75

24.75

10

10

10

10

TX_LANE_RATE

10

15

24.75

24.75

10

10

10

10

REF_CLK_RATE

250

375

375

—

375

—

—

—

DEVICE_CLK_RATE

250

375

—

—

—

—

—

—

RX_JESD_M

8

8

8

8

8

8

8

8

RX_JESD_L

4

8

8

8

4

4

4

4

RX_JESD_S

1

1

2

2

1

1

1

1

RX_JESD_NP

16

16

12

12

16

16

16

16

RX_NUM_LINKS

1

1

1

1

1

1

1

1

RX_TPL_WIDTH

—

—

—

—

—

—

—

{}

TX_JESD_M

8

8

8

8

8

8

8

8

TX_JESD_L

4

8

8

8

4

4

4

4

TX_JESD_S

1

1

2

2

1

1

1

1

TX_JESD_NP

16

16

12

12

16

16

16

16

TX_NUM_LINKS

1

1

1

1

1

1

1

1

TX_TPL_WIDTH

—

—

—

—

—

—

—

{}

TDD_SUPPORT

—

—

—

—

—

—

—

0

SHARED_DEVCLK

—

—

—

—

—

—

—

0

TDD_CHANNEL_CNT

—

—

—

—

—

—

—

2

TDD_SYNC_WIDTH

—

—

—

—

—

—

—

32

TDD_SYNC_INT

—

—

—

—

—

—

—

1

TDD_SYNC_EXT

—

—

—

—

—

—

—

0

TDD_SYNC_EXT_CDC

—

—

—

—

—

—

—

0

RX_KS_PER_CHANNEL

16

32

64

64

64

16384

—

—

TX_KS_PER_CHANNEL

16

32

64

64

64

16384

—

—

ADC_DO_MEM_TYPE

—

—

—

—

—

2

—

—

DAC_DO_MEM_TYPE

—

—

—

—

—

2

—

—

Parameter
Default value of the parameters

depending on carrier

VCK190

VPK180

VCU118

ZC706

ZCU102

JESD_MODE

64B66B

64B66B

8B10B

8B10B*

8B10B*

RX_LANE_RATE

24.75

24.75

15

10

15

TX_LANE_RATE

24.75

24.75

15

10

15

REF_CLK_RATE

375

375

—

—

—

RX_JESD_M

4

4

4

8

4

RX_JESD_L

8

8

8

4

8

RX_JESD_S

4

4

1

1

1

RX_JESD_NP

12

12

16

16

16

RX_NUM_LINKS

1

1

1

1

1

RX_TPL_WIDTH

—

—

—

—

{}

TX_JESD_M

4

4

4

8

4

TX_JESD_L

8

8

8

4

8

TX_JESD_S

8

8

1

1

1

TX_JESD_NP

12

12

16

16

16

TX_NUM_LINKS

1

1

1

1

1

TX_TPL_WIDTH

—

—

—

—

{}

RX_KS_PER_CHANNEL

64

64

64

—

—

TX_KS_PER_CHANNEL

64

64

64

—

—

Legend

* — for this carrier only the 8B10B mode is supported

The result of the build, if parameters were used, will be in a folder named by the configuration used:

if the following command was run

make RX_LANE_RATE=2.5 TX_LANE_RATE=2.5 RX_JESD_L=8 RX_JESD_M=4 RX_JESD_S=1 RX_JESD_NP=16 TX_JESD_L=8 TX_JESD_M=4 TX_JESD_S=1 TX_JESD_NP=16

then the folder name will be:

RXRATE2_5_TXRATE2_5_RXL8_RXM4_RXS1_RXNP16_TXL8_TXM4_TXS1_TXNP16 because of truncation of some keywords so the name will not exceed the limits of the Operating System (JESD, LANE, etc. are removed) of 260 characters.

A more comprehensive build guide can be found in the Build an HDL project user guide.

Software considerations

ADC - crossbar config

Due to physical constraints, Rx lanes are reordered as described in the following table.

e.g physical lane 2 from ADC connects to logical lane 7 from the FPGA. Therefore the crossbar from the device must be set accordingly.

ADC phy Lane

FPGA Rx lane / Logical Lane

0

2

1

0

2

7

3

6

4

5

5

4

6

3

7

1

DAC - crossbar config

Due to physical constraints, Tx lanes are reordered as described in the following table.

e.g physical lane 2 from DAC connects to logical lane 7 from the FPGA. Therefore the crossbar from the device must be set accordingly.

DAC phy lane

FPGA Tx lane / Logical lane

0

0

1

2

2

7

3

6

4

1

5

5

6

4

7

3

Resources

More information

Support

Analog Devices, Inc. will provide limited online support for anyone using the reference design with ADI components via the EngineerZone FPGA reference designs forum.

For questions regarding the ADI Linux device drivers, device trees, etc. from our Linux GitHub repository, the team will offer support on the EngineerZone Linux software drivers forum.

For questions concerning the ADI No-OS drivers, from our No-OS GitHub repository, the team will offer support on the EngineerZone microcontroller No-OS drivers forum.

It should be noted, that the older the tools’ versions and release branches are, the lower the chances to receive support from ADI engineers.