AXI AD7616#

The AXI AD7616 IP core can be used to interface the AD7616 device using an FPGA. The core has a AXI Memory Map interface for configuration, supports the parallel data interface of the device, and has a simple FIFO interface for the DMAC.

Files#

Name	Description
library/axi_ad7616/axi_ad7616.v	Verilog source for the AXI AD7616.
library/axi_ad7616/axi_ad7616_control.v	Verilog source for the AXI AD7616 control.
library/axi_ad7616/axi_ad7616_pif.v	Verilog source for the AXI AD7616 parallel interface.

Block Diagram#

Configuration Parameters#

Name	Description	Default Value	Choices/Range
`ID`	Core ID should be unique for each IP in the system	`0`

Interface#

s_axi

Standard AXI Slave Memory Map interface

Physical Port	Logical Port	Direction
`s_axi_awaddr`	`AWADDR`	in [15:0]
`s_axi_awprot`	`AWPROT`	in [2:0]
`s_axi_awvalid`	`AWVALID`	in
`s_axi_awready`	`AWREADY`	out
`s_axi_wdata`	`WDATA`	in [31:0]
`s_axi_wstrb`	`WSTRB`	in [3:0]
`s_axi_wvalid`	`WVALID`	in
`s_axi_wready`	`WREADY`	out
`s_axi_bresp`	`BRESP`	out [1:0]
`s_axi_bvalid`	`BVALID`	out
`s_axi_bready`	`BREADY`	in
`s_axi_araddr`	`ARADDR`	in [15:0]
`s_axi_arprot`	`ARPROT`	in [2:0]
`s_axi_arvalid`	`ARVALID`	in
`s_axi_arready`	`ARREADY`	out
`s_axi_rdata`	`RDATA`	out [31:0]
`s_axi_rresp`	`RRESP`	out [1:0]
`s_axi_rvalid`	`RVALID`	out
`s_axi_rready`	`RREADY`	in

s_axi_aclk

Physical Port	Logical Port	Direction	Dependency
`s_axi_aclk`	`CLK`	in

s_axi_aresetn

Physical Port	Logical Port	Direction	Dependency
`s_axi_aresetn`	`RST`	in

Ports

Physical Port	Direction	Description
`rx_cs_n`	out	Active low chip select
`rx_db_o`	out [15:0]	Parallel data out
`rx_db_i`	in [15:0]	Parallel data in
`rx_db_t`	out	Active high 3-state T pin for IOBUF
`rx_rd_n`	out	Active low parallel data read control
`rx_wr_n`	out	Active low parallel data write control
`rx_trigger`	in	End of conversion signal
`adc_valid`	out	Shows when a valid data is available on the bus
`adc_data`	out [15:0]	Data bus
`adc_sync`	out	Shows the first valid beat on a sequence

Register Map#

AXI AD7616 (axi_ad7616) register map

DWORD	BYTE	Reg Name				Description
		BITS	Field Name	Type	Default Value	Description
`0x100`	`0x400`	`VERSION`				Version and Scratch Registers.
		`[31:0]`	`VERSION`	`RO`	`0x00001002`	Version number
`0x101`	`0x404`	`ID`				Instance identifier number.
		`[31:0]`	`ID`	`RO`	`0x00000000`	Version number
`0x102`	`0x408`	`SCRATCH`				Scratch register.
		`[31:0]`	`SCRATCH`	`RW`	`0x00000000`	Version number
`0x110`	`0x440`	`UP_CNTRL`				ADC Interface Control & Status.
		`[1:1]`	`CNVST_EN`	`RW`	`0x0`	Enable the CNVST pulse generator of core.
		`[0:0]`	`RESETN`	`RW`	`0x0`	Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.
`0x111`	`0x444`	`UP_CONV_RATE`				ADC Interface Control & Status.
		`[31:0]`	`UP_CONV_RATE`	`RW`	`0x00000000`	Rate of the conversion pulse signal, it’s relative to the system clock (s_axis_clk).
`0x112`	`0x448`	`UP_BURST_LENGTH`				ADC Interface Control & Status.
		`[4:0]`	`UP_BURST_LENGTH`	`RW`	`0x00`	Define the actual burst length. The value must be equal to burst length - 1 . This register is active just on PARALLEL mode.
`0x113`	`0x44c`	`UP_READ_DATA`				ADC Interface Control & Status.
		`[31:0]`	`UP_READ_DATA`	`RO`	`0x00000000`	This register can be used to read the device registers on PARALLEL software mode.
`0x114`	`0x450`	`UP_WRITE_DATA`				ADC Interface Control & Status.
		`[31:0]`	`UP_WRITE_DATA`	`WO`	`0x00000000`	This register can be used to write the device registers on PARALLEL software mode.

Access Type	Name	Description
RO	Read-only	Reads will return the current register value. Writes have no effect.
RW	Read-write	Reads will return the current register value. Writes will change the current register value.
WO	Write-only	Writes will change the current register value. Reads have no effect.

Software Support#

Linux documentation on wiki
No-OS driver at drivers/adc/ad7616

Refereces#

HDL IP core at library/axi_ad7616
HDL project at projects/ad7616_sdz
HDL project documentation at AD7616-SDZ HDL project
AD7616