AXI ADC Decimate

The AXI ADC Decimate IP core allows decimating the input data by 10/100/1000/10000/100000, with filtering and arbitrary decimation by dropping samples.

More about the generic framework interfacing ADCs can be read here at Generic AXI ADC.

Important

The axi_adc_decimate was designed to interface with 12-bit converters. Even though the input data bus width is 16, it will not work with anything higher than 12-bit sign extended (to 16-bit) data.

Features

AXI Lite control/status interface
Allows decimation by 10/100/1000/10000/100000 with filtering
Allows arbitrary decimation by dropping samples
Filtering is implemented by a 6-section CIC programmable rate filter and a compensation FIR filter.

Files

Name	Description
library/axi_adc_decimate/axi_adc_decimate.v	Verilog source for the peripheral.

Block Diagram

Configuration Parameters

Name	Description	Default Value	Choices/Range
`CORRECTION_DISABLE`	Disable scale correction of the CIC output	`1`

Interface

s_axi

Standard AXI Slave Memory Map interface

Physical Port	Logical Port	Direction
`s_axi_awaddr`	`AWADDR`	in [6:0]
`s_axi_awprot`	`AWPROT`	in [2:0]
`s_axi_awvalid`	`AWVALID`	in
`s_axi_awready`	`AWREADY`	out
`s_axi_wdata`	`WDATA`	in [31:0]
`s_axi_wstrb`	`WSTRB`	in [3:0]
`s_axi_wvalid`	`WVALID`	in
`s_axi_wready`	`WREADY`	out
`s_axi_bresp`	`BRESP`	out [1:0]
`s_axi_bvalid`	`BVALID`	out
`s_axi_bready`	`BREADY`	in
`s_axi_araddr`	`ARADDR`	in [6:0]
`s_axi_arprot`	`ARPROT`	in [2:0]
`s_axi_arvalid`	`ARVALID`	in
`s_axi_arready`	`ARREADY`	out
`s_axi_rdata`	`RDATA`	out [31:0]
`s_axi_rresp`	`RRESP`	out [1:0]
`s_axi_rvalid`	`RVALID`	out
`s_axi_rready`	`RREADY`	in

s_axi_aclk

Physical Port	Logical Port	Direction	Dependency
`s_axi_aclk`	`CLK`	in

s_axi_aresetn

Physical Port	Logical Port	Direction	Dependency
`s_axi_aresetn`	`RST`	in

adc_clk

Clock input

Physical Port	Logical Port	Direction	Dependency
`adc_clk`	`CLK`	in

adc_rst

Reset, synchronous on the adc_clk clock domain

Physical Port	Logical Port	Direction	Dependency
`adc_rst`	`RST`	in

Ports

Physical Port	Direction	Description
`adc_data_a`	in [15:0]	Analog data for channel A
`adc_data_b`	in [15:0]	Analog data for channel B
`adc_valid_a`	in	Data valid signal for channel A
`adc_valid_b`	in	Data valid signal for channel B
`adc_dec_data_a`	out [15:0]	Decimated data for channel A
`adc_dec_data_b`	out [15:0]	Decimated data for channel B
`adc_dec_valid_a`	out	Data valid for channel A
`adc_dec_valid_b`	out	Data valid for channel B
`adc_data_rate`	out [2:0]	Data rate (decimation ratio)
`adc_oversampling_en`	out	Data oversampling enabled

Detailed Description

For some applications, the maximum sampling rate is not required and leads to lots of samples transferred to memory. To avoid it, the decimation IP can be used.

The decimation block allows decimating the input data so that the sampling frequency can be reduced by 10, 100, 1000, 10000, 100000, with filtering.

The filtering is implemented by a 6-section CIC programmable rate filter which allows decimation by 5/50/500/5000/50000 and a compensation FIR filter (decimation by 2).

At the end of the filter chain, there is an arbitrary decimation block. The arbitrary decimation can be activated independently and it does not implement any type of filtering.

Register Map

Analog Decimation (axi_adc_decimate) register map

DWORD	BYTE	Reg Name				Description
		BITS	Field Name	Type	Default Value	Description
`0x0`	`0x0`	`VERSION`				Version of the peripheral. Follows semantic versioning. Current version 1.0.0.
		`[31:16]`	`VERSION_MAJOR`	`RO`	`0x0001`
		`[15:8]`	`VERSION_MINOR`	`RO`	`0x00`
		`[7:0]`	`VERSION_PATCH`	`RO`	`0x00`
`0x1`	`0x4`	`SCRATCH`
		`[31:0]`	`SCRATCH`	`RW`	`0x00000000`	Scratch register useful for debug.
`0x10`	`0x40`	`DECIMATION_RATIO`				Control Arbitrary Decimation Ratio.
		`[31:0]`	`DECIMATION_RATIO`	`RW`	`0x00000000`	Set the arbitrary decimation ratio at the end of the decimation chain. Simply drop samples.
`0x11`	`0x44`	`DECIMATION_STAGE_ENABLE`				Control Filtered Decimation.
		`[2:0]`	`FILTERED_DECIMATION_RATIO`	`RW`	`0x0`	Enables the filtered decimation: 0: No filtered decimation 1: Decimation by 10. Result should be corrected by a 1.05 factor 2: Decimation by 100. Result should be corrected by a 1.1 factor 3: Decimation by 1000. Result should be corrected by a 1.15 factor 6: Decimation by 10000. Result should be corrected by a 1.2 factor 7: Decimation by 100000. Result should be corrected by a 1.26 factor default: No filtered decimation
`0x12`	`0x48`	`CONFIG`				Configuration Register
		`[1]`	`CORRECTION_ENABLE_B`	`RW`	`0x0`	If set to 1, correction is enabled on channel B. The decimated data will be multiplied with the value from the CORRECTION_COEFFICIENT_B register.
		`[0]`	`CORRECTION_ENABLE_A`	`RW`	`0x0`	If set to 1, correction is enabled on channel A. The decimated data will be multiplied with the value from the CORRECTION_COEFFICIENT_A register.
`0x13`	`0x4c`	`CORRECTION_COEFFICIENT_A`				Correction Coefficient A
		`[15:0]`	`CORRECTION_COEFFICIENT`	`RW`	`0x0000`	Scale correction (if equipped) coefficient for channel A. The format is 1.1.14 (sign, integer and fractional bits). Allows for correction of the CIC filter amplification.
`0x14`	`0x50`	`CORRECTION_COEFFICIENT_B`				Correction Coefficient B
		`[15:0]`	`CORRECTION_COEFFICIENT`	`RW`	`0x0000`	Scale correction (if equipped) coefficient for channel B. The format is 1.1.14 (sign, integer and fractional bits). Allows for correction of the CIC filter amplification.

Access Type	Name	Description
RO	Read-only	Reads will return the current register value. Writes have no effect.
RW	Read-write	Reads will return the current register value. Writes will change the current register value.