AD9467-FMC HDL project

Overview

The AD9467 chip used on EVAL-AD9467 is a 16-bit, monolithic, IF sampling analog-to-digital converter (ADC) with a conversion rate of up to 250 MSPS. This reference design includes a data capture interface and the external DDR-DRAM interface for sample storage. It allows programming the device and monitoring its internal status registers. The board also provides other options to drive the clock and analog inputs of the ADC. This can be done by programming the AD9517-4 clock chip and/or setting up the ADL5565 differential amplifier, respectively.

Supported boards

AD9467-FMC-250EBZ also referred to as EVAL-AD9467

Supported devices

AD9467

Supported carriers

KC705 LPC slot
ZedBoard

Block design

The PN9/PN23 sequences are not compatible with O.150. Please use the equations given in the reference design. They follow the polynomial equations as in O.150, but ONLY the MSB is inverted.

The AD9467 drives the interleaved first byte (D15:D1) on the rising edge and second byte (D14:D0) on the falling edge of DCO clock. However, in certain frequencies the captured data (from IDDR) seems to be reverse. If that occurs, try setting the “capture select” bit (register 0x0A, bit to 0).

Block diagram

Project block diagram

The data path and clock domains are depicted in the below diagram:

AD9467 FMC card block diagram

The block diagram of the AD9467-FMC evaluation board is depicted below:

The reference design is built on an ARM/Microblaze based system tailored for Linux.

Through an SPI interface, the software can access the AD9467/AD9517-4 registers, given the possibility to initialize and configure the ADC and/or clock chip.

The LVDS interface captures and buffers data from the ADC. The DMA interface then transfers the samples to the external DDR-DRAM. The capture is initiated by the software. The status of capture (overflow, over the range) are reported back to the software.

Clock selection

The board provides 3 possible clock paths for clocking the AD9467 (some of them require hardware changes), as follows:

Default clock input

The default clock input circuitry is derived from a simple transformer-coupled circuit using a high bandwidth 1:1 impedance ratio transformer (T201) that adds a very low amount of jitter to the clock path. The clock input (J201) is 50 Ohm terminated and AC-coupled to handle single-ended sine wave types of inputs. The transformer converts the single-ended input to a differential signal that is clipped before entering the ADC clock inputs.

Crystal oscillator

The evaluation board can be set up to be clocked from the crystal oscillator, Y200. This oscillator is a low phase noise oscillator from Vectron (VCC6-QCD-250M000).

Install C205 and C206
Remove C202

Jumper P200 is used to disable the oscillator from running.

Clock generator AD9517

A differential LVPECL or LVDS clock driver can also be used to clock the ADC input using the AD9517.

Populate (C304, C305) for LVPECL clock driver or (C306, C307) for
LVDS clock driver, with 0.1 µF capacitors
Remove C209 and C210 to disconnect the default clock path inputs

The AD9517 has many SPI-selectable options that are set to a default mode of operation. Consult the AD9517 data sheet for more information about these and other options.

Warning

Please make sure you have removed or inserted the appropriate components on the board to select the desired clock path.

C302 and C303 are not installed as indicated in the Schematic and BOM.

CPU/Memory interconnects addresses

The addresses are dependent on the architecture of the FPGA, having an offset added to the base address from HDL (see more at CPU/Memory interconnects addresses).

Instance	Zynq/Microblaze
axi_ad9467	0x44A0_0000
axi_ad9467_dma	0x44A3_0000

SPI connections

Depending on the carrier, the SPI connections are as follows:

SPI type	SPI manager instance	SPI subordinate	CS
PS	spi0	AD9467	0
MicroBlaze	spi_*	AD9467	0

Interrupts

Below are the Programmable Logic interrupts used in this project.

Instance name	HDL PS	HDL MB	Linux Zynq	Actual Zynq	Linux MB
axi_ad9467_dma	13	12	57	89	12

Building the HDL project

The design is built upon ADI’s generic HDL reference design framework. ADI distributes the bit/elf files of these projects as part of the ADI Kuiper Linux. If you want to build the sources, ADI makes them available on the HDL repository. To get the source you must clone the HDL repository.

Then go to the projects/ad9467_fmc location and run the make command by typing in your command prompt:

Linux/Cygwin/WSL

~$

cd hdl/projects/ad9467_fmc/zed

~/hdl/projects/ad9467_fmc/zed$

make

A more comprehensive build guide can be found in the Build an HDL project user guide.

Resources

HDL related

AD9467_FMC HDL project source code

IP name	Source code link	Documentation link
AXI_AD9467	library/axi_ad9467	AXI AD9467
AXI_CLKGEN	library/axi_clkgen	AXI CLK Generator
AXI_DMAC	library/axi_dmac	AXI DMAC
AXI_HDMI_TX	library/axi_hdmi_tx	AXI HDMI TX
AXI_I2S_ADI	library/axi_i2s_adi	—
AXI_SPDIF_TX	library/axi_spdif_tx	—
AXI_SYSID	library/axi_sysid	AXI System ID
SYSID_ROM	library/sysid_rom	AXI System ID
UTIL_I2C_MIXER	library/util_i2c_mixer	—

More information

ADI HDL User guide

Support

Analog Devices, Inc. will provide limited online support for anyone using the reference design with ADI components via the EngineerZone FPGA reference designs forum.

For questions regarding the ADI Linux device drivers, device trees, etc. from our Linux GitHub repository, the team will offer support on the EngineerZone Linux software drivers forum.

For questions concerning the ADI No-OS drivers, from our No-OS GitHub repository, the team will offer support on the EngineerZone microcontroller No-OS drivers forum.

It should be noted, that the older the tools’ versions and release branches are, the lower the chances to receive support from ADI engineers.