Corundum

The Corundum IP core repackages Corundum NIC as an IP Core.

Features

• AXI-based configuration

• Vivado compatible

Files

Name	Description
library/corundum/corundum.v	Verilog source for the Corundum top module.
library/corundum/corundum_ip.tcl	TCL script to generate the Vivado IP-integrator project.

Configuration Parameters

Name	Description	Default Value	Choices/Range
FPGA_ID	Fpga Id.	'h04A49093
FW_ID	Fw Id.	'h00000000
FW_VER	Fw Ver.	'h00000100
BOARD_ID	Board Id.	'h10EE9104
BOARD_VER	Board Ver.	'h01000000
BUILD_DATE	Build Date.	'h23F0AF00
GIT_HASH	Git Hash.	'hDCE357BF
RELEASE_INFO	Release Info.	'h00000000
TDMA_BER_ENABLE	Tdma Ber Enable.	0
IF_COUNT	If Count.	1
PORTS_PER_IF	Ports Per If.	1
SCHED_PER_IF	Sched Per If.	1
PORT_MASK	Port Mask.	0
CLK_PERIOD_NS_NUM	Clk Period Ns Num.	4
CLK_PERIOD_NS_DENOM	Clk Period Ns Denom.	1
PTP_CLOCK_PIPELINE	Ptp Clock Pipeline.	0
PTP_CLOCK_CDC_PIPELINE	Ptp Clock Cdc Pipeline.	0
PTP_PORT_CDC_PIPELINE	Ptp Port Cdc Pipeline.	0
PTP_PEROUT_ENABLE	Ptp Perout Enable.	1
PTP_PEROUT_COUNT	Ptp Perout Count.	1
EVENT_QUEUE_OP_TABLE_SIZE	Event Queue Op Table Size.	32
TX_QUEUE_OP_TABLE_SIZE	Tx Queue Op Table Size.	32
RX_QUEUE_OP_TABLE_SIZE	Rx Queue Op Table Size.	32
CQ_OP_TABLE_SIZE	Cq Op Table Size.	32
EQN_WIDTH	Eqn Width.	5
TX_QUEUE_INDEX_WIDTH	Tx Queue Index Width.	13
RX_QUEUE_INDEX_WIDTH	Rx Queue Index Width.	8
CQN_WIDTH	Cqn Width.	14
EQ_PIPELINE	Eq Pipeline.	3
TX_QUEUE_PIPELINE	Tx Queue Pipeline.	4
RX_QUEUE_PIPELINE	Rx Queue Pipeline.	3
CQ_PIPELINE	Cq Pipeline.	5
TX_DESC_TABLE_SIZE	Tx Desc Table Size.	32
RX_DESC_TABLE_SIZE	Rx Desc Table Size.	32
RX_INDIR_TBL_ADDR_WIDTH	Rx Indir Tbl Addr Width.	8
TX_SCHEDULER_OP_TABLE_SIZE	Tx Scheduler Op Table Size.	32
TX_SCHEDULER_PIPELINE	Tx Scheduler Pipeline.	4
TDMA_INDEX_WIDTH	Tdma Index Width.	6
PTP_TS_ENABLE	Ptp Ts Enable.	1
TX_CPL_FIFO_DEPTH	Tx Cpl Fifo Depth.	32
TX_CHECKSUM_ENABLE	Tx Checksum Enable.	1
RX_HASH_ENABLE	Rx Hash Enable.	1
RX_CHECKSUM_ENABLE	Rx Checksum Enable.	1
TX_FIFO_DEPTH	Tx Fifo Depth.	16384
RX_FIFO_DEPTH	Rx Fifo Depth.	16384
MAX_TX_SIZE	Max Tx Size.	9214
MAX_RX_SIZE	Max Rx Size.	9214
TX_RAM_SIZE	Tx Ram Size.	16384
RX_RAM_SIZE	Rx Ram Size.	16384
APP_ID	App Id.	'h00000000
APP_ENABLE	App Enable.	0
APP_CTRL_ENABLE	App Ctrl Enable.	1
APP_DMA_ENABLE	App Dma Enable.	1
APP_AXIS_DIRECT_ENABLE	App Axis Direct Enable.	1
APP_AXIS_SYNC_ENABLE	App Axis Sync Enable.	1
APP_AXIS_IF_ENABLE	App Axis If Enable.	1
APP_STAT_ENABLE	App Stat Enable.	1
AXI_DATA_WIDTH	Axi Data Width.	128
AXI_ADDR_WIDTH	Axi Addr Width.	32
AXI_STRB_WIDTH	Axi Strb Width.	16
AXI_ID_WIDTH	Axi Id Width.	8
DMA_IMM_ENABLE	Dma Imm Enable.	0
DMA_IMM_WIDTH	Dma Imm Width.	32
DMA_LEN_WIDTH	Dma Len Width.	16
DMA_TAG_WIDTH	Dma Tag Width.	16
RAM_ADDR_WIDTH	Ram Addr Width.	14
RAM_PIPELINE	Ram Pipeline.	2
AXI_DMA_MAX_BURST_LEN	Axi Dma Max Burst Len.	256
IRQ_COUNT	Irq Count.	32
IRQ_STRETCH	Irq Stretch.	10
AXIL_CTRL_DATA_WIDTH	Axil Ctrl Data Width.	32
AXIL_CTRL_ADDR_WIDTH	Axil Ctrl Addr Width.	24
AXIL_CTRL_STRB_WIDTH	Axil Ctrl Strb Width.	4
AXIL_APP_CTRL_DATA_WIDTH	Axil App Ctrl Data Width.	32
AXIL_APP_CTRL_ADDR_WIDTH	Axil App Ctrl Addr Width.	24
AXIL_APP_CTRL_STRB_WIDTH	Axil App Ctrl Strb Width.	4
AXIS_ETH_TX_PIPELINE	Axis Eth Tx Pipeline.	0
AXIS_ETH_TX_FIFO_PIPELINE	Axis Eth Tx Fifo Pipeline.	2
AXIS_ETH_TX_TS_PIPELINE	Axis Eth Tx Ts Pipeline.	0
AXIS_ETH_RX_PIPELINE	Axis Eth Rx Pipeline.	0
AXIS_ETH_RX_FIFO_PIPELINE	Axis Eth Rx Fifo Pipeline.	2
STAT_ENABLE	Stat Enable.	1
STAT_DMA_ENABLE	Stat Dma Enable.	1
STAT_AXI_ENABLE	Stat Axi Enable.	1
STAT_INC_WIDTH	Stat Inc Width.	24
STAT_ID_WIDTH	Stat Id Width.	12

Interface

m_axi_dma

Physical Port	Logical Port	Direction	Dependency
m_axi_dma_awid	AWID	out [7:0]
m_axi_dma_awaddr	AWADDR	out [31:0]
m_axi_dma_awlen	AWLEN	out [7:0]
m_axi_dma_awsize	AWSIZE	out [2:0]
m_axi_dma_awuser	AWUSER	out
m_axi_dma_awburst	AWBURST	out [1:0]
m_axi_dma_awlock	AWLOCK	out
m_axi_dma_awcache	AWCACHE	out [3:0]
m_axi_dma_awprot	AWPROT	out [2:0]
m_axi_dma_awqos	AWQOS	out [3:0]
m_axi_dma_awvalid	AWVALID	out
m_axi_dma_awready	AWREADY	in
m_axi_dma_wdata	WDATA	out [127:0]
m_axi_dma_wstrb	WSTRB	out [15:0]
m_axi_dma_wlast	WLAST	out
m_axi_dma_wvalid	WVALID	out
m_axi_dma_wready	WREADY	in
m_axi_dma_bid	BID	in [7:0]
m_axi_dma_bresp	BRESP	in [1:0]
m_axi_dma_bvalid	BVALID	in
m_axi_dma_bready	BREADY	out
m_axi_dma_arid	ARID	out [7:0]
m_axi_dma_araddr	ARADDR	out [31:0]
m_axi_dma_arlen	ARLEN	out [7:0]
m_axi_dma_arsize	ARSIZE	out [2:0]
m_axi_dma_aruser	ARUSER	out
m_axi_dma_arburst	ARBURST	out [1:0]
m_axi_dma_arlock	ARLOCK	out
m_axi_dma_arcache	ARCACHE	out [3:0]
m_axi_dma_arprot	ARPROT	out [2:0]
m_axi_dma_arqos	ARQOS	out [3:0]
m_axi_dma_arvalid	ARVALID	out
m_axi_dma_arready	ARREADY	in
m_axi_dma_rid	RID	in [7:0]
m_axi_dma_rdata	RDATA	in [127:0]
m_axi_dma_rresp	RRESP	in [1:0]
m_axi_dma_rlast	RLAST	in
m_axi_dma_rvalid	RVALID	in
m_axi_dma_rready	RREADY	out

s_axil_app_ctrl

Physical Port	Logical Port	Direction	Dependency
s_axil_app_ctrl_awaddr	AWADDR	in [23:0]
s_axil_app_ctrl_awprot	AWPROT	in [2:0]
s_axil_app_ctrl_awvalid	AWVALID	in [0:0]
s_axil_app_ctrl_awready	AWREADY	out [0:0]
s_axil_app_ctrl_wdata	WDATA	in [31:0]
s_axil_app_ctrl_wstrb	WSTRB	in [3:0]
s_axil_app_ctrl_wvalid	WVALID	in [0:0]
s_axil_app_ctrl_wready	WREADY	out [0:0]
s_axil_app_ctrl_bresp	BRESP	out [1:0]
s_axil_app_ctrl_bvalid	BVALID	out [0:0]
s_axil_app_ctrl_bready	BREADY	in [0:0]
s_axil_app_ctrl_araddr	ARADDR	in [23:0]
s_axil_app_ctrl_arprot	ARPROT	in [2:0]
s_axil_app_ctrl_arvalid	ARVALID	in [0:0]
s_axil_app_ctrl_arready	ARREADY	out [0:0]
s_axil_app_ctrl_rdata	RDATA	out [31:0]
s_axil_app_ctrl_rresp	RRESP	out [1:0]
s_axil_app_ctrl_rvalid	RVALID	out [0:0]
s_axil_app_ctrl_rready	RREADY	in [0:0]

s_axil_ctrl

Physical Port	Logical Port	Direction	Dependency
s_axil_ctrl_awaddr	AWADDR	in [23:0]
s_axil_ctrl_awprot	AWPROT	in [2:0]
s_axil_ctrl_awvalid	AWVALID	in [0:0]
s_axil_ctrl_awready	AWREADY	out [0:0]
s_axil_ctrl_wdata	WDATA	in [31:0]
s_axil_ctrl_wstrb	WSTRB	in [3:0]
s_axil_ctrl_wvalid	WVALID	in [0:0]
s_axil_ctrl_wready	WREADY	out [0:0]
s_axil_ctrl_bresp	BRESP	out [1:0]
s_axil_ctrl_bvalid	BVALID	out [0:0]
s_axil_ctrl_bready	BREADY	in [0:0]
s_axil_ctrl_araddr	ARADDR	in [23:0]
s_axil_ctrl_arprot	ARPROT	in [2:0]
s_axil_ctrl_arvalid	ARVALID	in [0:0]
s_axil_ctrl_arready	ARREADY	out [0:0]
s_axil_ctrl_rdata	RDATA	out [31:0]
s_axil_ctrl_rresp	RRESP	out [1:0]
s_axil_ctrl_rvalid	RVALID	out [0:0]
s_axil_ctrl_rready	RREADY	in [0:0]

iic

Physical Port	Logical Port	Direction	Dependency
scl_i	SCL_I	in
scl_o	SCL_O	out
scl_t	SCL_T	out
sda_i	SDA_I	in
sda_o	SDA_O	out
sda_t	SDA_T	out

Ports

Physical Port	Direction	Dependency	Description
core_clk	in		Buses m_axi_dma, s_axil_app_ctrl, s_axil_ctrl are synchronous to this clock domain.
core_rst	in [0:0]		Buses m_axi_dma, s_axil_app_ctrl, s_axil_ctrl are synchronous to this reset signal.
core_irq	out [31:0]
led	out [1:0]
sfp_led	out [1:0]
sfp_rx_p	in
sfp_rx_n	in
sfp_tx_p	out
sfp_tx_n	out
sfp_mgt_refclk_p	in
sfp_mgt_refclk_n	in
sfp_tx_disable	out
sfp_tx_fault	in
sfp_rx_los	in
sfp_mod_abs	in

Building

This project uses Corundum NIC and it needs to be cloned alongside this repository.

hdl/../> git clone https://github.com/corundum/corundum.git
hdl/../corundum/> git checkout ed4a26e2cbc0a429c45d5cd5ddf1177f86838914
hdl/library/corundum> make &

Publications

The following papers pertain to the Corundum source code:

• J- A. Forencich, A. C. Snoeren, G. Porter, G. Papen, Corundum: An Open-Source 100-Gbps NIC, in FCCM’20. (FCCM Paper, FCCM Presentation)

• J- A. Forencich, System-Level Considerations for Optical Switching in Data Center Networks. (Thesis)

References

• HDL IP core at library/corundum

• HDL project at projects/ad_gmsl2eth_sl

• AD-GMSL2ETH-SL HDL project

• AD-GMSL2ETH-SL