CN0585 HDL project#

Overview#

The EVAL-CN0585-FMCZ Low Latency Development Kit (LLDK) board is a development board consisting of 4 x 16-bit ADC channels and 4 x 16-bit DAC channels that are interfaced with an FPGA through the FMC Low Pin Count (LPC) Connector. Current revision of EVAL-CN0585-FMCZ is Rev B. EVAL-CN0585-FMCZ, EVAL-CN0585-FMCZ and - ZedBoard are connected together to build a development system setup.

Supported boards#

Supported devices#

Supported carriers#

Evaluation board

Carrier

FMC slot

CN0585 + CN0584

ZedBoard

FMC-LPC

Block design#

The architecture is composed of two AD3552R digital-to-analog converter interface IPs and four LTC2387-16 analog-to-digital converter interface IPs. All these IPs utilize an 120MHz reference clock, which is produced by an axi_clkgen IP.

Block diagram#

The data path and clock domains are depicted in the below diagram:

CN0585/ZedBoard block diagram

CPU/Memory interconnects addresses#

The addresses are dependent on the architecture of the FPGA, having an offset added to the base address from HDL (see more at HDL Architecture).

Instance

Address Zynq/Microblaze

axi_ltc2387_0

0X44A0_0000

axi_ltc2387_1

0X44A1_0000

axi_ltc2387_2

0X44A2_0000

axi_ltc2387_3

0X44A3_0000

axi_ltc2387_dma

0X44A4_0000

axi_clkgen

0X44B0_0000

axi_pwm_gen

0X44B1_0000

max_spi

0X44B2_0000

axi_ad3552r_0

0X44D0_0000

axi_dac_0_dma

0X44D3_0000

axi_ad3552r_1

0X44E0_0000

axi_dac_1_dma

0X44E3_0000

I2C connections#

I2C type

I2C manager instance

Alias

Address

I2C subordinate

PL

iic_fmc

axi_iic_fmc

0x4162_0000

PL

iic_main

axi_iic_main

0x4160_0000

SPI connections#

SPI type

SPI manager instance

SPI subordinate

CS

PL

max_spi

MAX7301

0

GPIOs#

GPIO signal

Direction

HDL GPIO EMIO

Software GPIO

Software GPIO

(from FPGA view)

Zynq-7000

Zynq MP

reset

INOUT

36

90

114

dac_0_ldac

INOUT

35

89

113

dac_1_ldac

INOUT

34

88

112

dac_1_alert

IN

33

87

111

dac_0_alert

IN

32

86

110

Interrupts#

Below are the Programmable Logic interrupts used in this project.

Instance name

HDL

Linux Zynq

Actual Zynq

axi_ltc2387_dma

13

57

89

max_spi

8

52

84

axi_dac_0_dma

5

34

66

axi_dac_1_dma

4

33

65

Building the HDL project#

The design is built upon ADI’s generic HDL reference design framework. ADI does not distribute the bit/elf files of these projects so they must be built from the sources available here. To get the source you must clone the HDL repository.

1user@analog:~$ cd hdl/projects/cn0585/zed
2user@analog:~/hdl/projects/cn0585/zed$ make

A more comprehensive build guide can be found in the Build a HDL project user guide.

Resources#

More information#

Support#

Analog Devices, Inc. will provide limited online support for anyone using the reference design with ADI components via the EngineerZone FPGA reference designs forum.

For questions regarding the ADI Linux device drivers, device trees, etc. from our Linux GitHub repository, the team will offer support on the EngineerZone Linux software drivers forum.

For questions concerning the ADI No-OS drivers, from our No-OS GitHub repository, the team will offer support on the EngineerZone microcontroller No-OS drivers forum.

It should be noted, that the older the tools’ versions and release branches are, the lower the chances to receive support from ADI engineers.