AD7616-SDZ HDL project#

Overview#

The AD7616 is a 16-bit, data acquisition system (DAS) that supports dual simultaneous sampling of 16 channels. It operates from a single 5 V supply and can accommodate ±10 V, ±5 V, and ±2.5 V true bipolar input signals while sampling at throughput rates up to 1 MSPS per channel pair with 90 dB SNR. Higher SNR performance can be achieved with the on-chip oversampling mode; 92 dB for an oversampling ratio of 2.

The input clamp protection circuitry can tolerate voltages up to ±20 V. The AD7616 has 1 MΩ analog input impedance regardless of sampling frequency. The single supply operation, on-chip filtering, and high input impedance eliminate the need for driver op-amps and external bipolar supplies.

Each device contains analog input clamp protection, a dual, 16-bit charge redistribution successive approximation analog-to-digital converter (ADC), a flexible digital filter, a 2.5 V reference and reference buffer, and high-speed serial and parallel interfaces.

Supported boards#

Supported devices#

Supported carriers#

Other required hardware#

Block design#

The data path of the HDL design is simple as follows:

  • the parallel interface is controlled by the axi_ad7616 IP core

  • the serial interface is controlled by the SPI Engine Framework

  • data is written into memory by a DMA (axi_dmac core)

  • all the control pins of the device are driven by GPIOs

Block diagram#

The data path and clock domains are depicted in the below diagrams:

AD7616_SDZ serial interface#

AD7616_SDZ using the serial interface block diagram

AD7616_SDZ parallel interface#

AD7616_SDZ using the parallel interface block diagram

Configuration modes#

The SER_PAR_N configuration parameter defines the interface type (Serial or Parallel). By default it is set to 1. Depending on the required interface mode, some hardware modifications need to be done on the board and/or make command:

In case of the PARALLEL interface:

make SER_PAR_N=0

In case of the SERIAL interface:

make SER_PAR_N=1

Note

This switch is a hardware switch. Please rebuild the design if the variable has been changed.

  • SL5 - unmounted - Parallel interface

  • SL5 - mounted - Serial interface

Jumper setup#

Jumper/Solder link

Position

Description

SL1

Unmounted

Channel Sequencer Enable

SL2

Unmounted

RC Enable Input

SL3

Mounted

Selects 2 MISO mode

SL4

Unmounted

Oversampling Ratio Selection OS2

SL5

Mounted

If mounted, selects serial interface

SL6

Unmounted

Oversampling Ratio Selection OS1

SL7

Unmounted

Oversampling Ratio Selection OS0

LK40

A

Onboard 5v0 power supply selected

LK41

A

Onboard 3v3 power supply selected

CPU/Memory interconnects addresses#

The addresses are dependent on the architecture of the FPGA, having an offset added to the base address from HDL(see more at HDL Architecture).

Instance

Address

axi_ad7616_dma

0x44A3_0000

spi_clkgen

0x44A7_0000

ad7616_pwm_gen

0x44B0_0000

spi_ad7616_axi_regmap **

0x44A0_0000

axi_ad7616 *

0x44A8_0000

Legend

  • * instantiated only for SER_PAR_N=0 (parallel interface)

  • ** instantiated only for SER_PAR_N=1 (serial interface)

I2C connections#

I2C type

I2C manager instance

Alias

Address

I2C subordinate

PL

iic_fmc

axi_iic_fmc

0x4162_0000

PL

iic_main

axi_iic_main

0x4160_0000

SPI connections#

SPI type

SPI manager instance

SPI subordinate

CS

PL

axi_spi_engine

AD7616

0

GPIOs#

The Software GPIO number is calculated as follows:

  • Zynq-7000: if PS7 is used, then offset is 54

GPIO signal

Direction

HDL GPIO EMIO

Software GPIO

(from FPGA view)

Zynq-7000

adc_reset_n

OUT

43

97

adc_hw_rngsel[1:0]

OUT

42:41

96:95

adc_os[2:0] **

OUT

40:38

94:92

adc_seq_en

OUT

37

91

adc_burst **

OUT

36

90

adc_chsel[2:0]

OUT

35:33

89:87

adc_crcen **

OUT

32

86

Legend

  • ** instantiated only for SER_PAR_N=1 (serial interface)

Interrupts#

Below are the Programmable Logic interrupts used in this project.

Instance name

HDL

Linux Zynq

Actual Zynq

axi_ad7616_dma

13

57

89

spi_ad7616 **

12

56

88

axi_ad7616 *

10

54

87

Legend

  • * instantiated only for SER_PAR_N=0 (parallel interface)

  • ** instantiated only for SER_PAR_N=1 (serial interface)

Building the HDL project#

The design is built upon ADI’s generic HDL reference design framework. ADI does not distribute the bit/elf files of these projects so they must be built from the sources available here. To get the source you must clone the HDL repository, and then build the project as follows:.

Linux/Cygwin/WSL

1user@analog:~$ cd hdl/projects/ad7616_sdz/zed
2user@analog:~/hdl/projects/ad7616_sdz/zed$ make SER_PAR_N=0

The result of the build, if parameters were used, will be in a folder named by the configuration used:

if the following command was run

make SER_PAR_N=0

then the folder name will be:

SERPARN0

A more comprehensive build guide can be found in the Build a HDL project user guide.

Connections and hardware changes#

Warning

The following hardware changes are required:

(Please note: Because of the SDP-I-FMC the level of the VADJ in the carrier board needs to be set to 3.3V.

Depending on the required interface mode, some hardware modifications need to be done.

  • SL5 - unmounted - Parallel interface

  • SL5 - mounted - Serial interface

Resources#

More information#

Support#

Analog Devices, Inc. will provide limited online support for anyone using the reference design with ADI components via the EngineerZone FPGA reference designs forum.

For questions regarding the ADI Linux device drivers, device trees, etc. from our Linux GitHub repository, the team will offer support on the EngineerZone Linux software drivers forum.

For questions concerning the ADI No-OS drivers, from our No-OS GitHub repository, the team will offer support on the EngineerZone microcontroller No-OS drivers forum.

It should be noted, that the older the tools’ versions and release branches are, the lower the chances to receive support from ADI engineers.