AXI AD3552R

The AXI AD3552R IP core can be used to interface the AD3552R, a low drift, ultra-fast, 16-bit accuracy, current output digital-to-analog converter (DAC) that can be configured in multiple voltage span ranges.

Features

  • AXI-based configuration

  • Vivado compatible

  • 8b register read/write SDR/DDR

  • 16b register read/write SDR/DDR

  • data stream SDR/DDR ( clk_in/8 or clk_in/4 update rate)

  • selectable input source: DMA/ADC/TEST_RAMP

  • data out clock(SCLK) has clk_in/8 frequency when the converter is configured and clk_in/2 when the converter is in stream mode

  • the IP reference clock (clk_in) can have a maximum frequency of 132MHz

  • the IP has multiple device synchronization capability when the DMA is set as an input data source

Files

Name

Description

library/axi_ad3552r/axi_ad3552r.v

Verilog source for the AXI AD3552R.

library/axi_ad3552r/axi_ad3552r_channel.v

Verilog source for the AXI AD3552R channel.

library/axi_ad3552r/axi_ad3552r_core.v

Verilog source for the AXI AD3552R core.

library/axi_ad3552r/axi_ad3552r_if.v

Verilog source for the AD3552R interface module.

library/axi_ad3552r/axi_ad3552r_if_tb.v

Verilog source for the AD3552R interface module testbench.

library/axi_ad3552r/axi_ad3552r_if_tb

Setup script for the AD3552R interface module testbench.

library/axi_ad3552r/axi_ad3552r_ip.tcl

TCL script to generate the Vivado IP-integrator project.

Block Diagram

AXI AD3552R block diagram

Configuration Parameters

Name

Description

Default Value

Choices/Range
ID

Core ID should be unique for each IP in the system - 0

 0

FPGA_TECHNOLOGY

Encoded value describing the technology/generation of the FPGA device (Arria 10/7series)

 0

Unknown (0), 7series (1), ultrascale (2), ultrascale+ (3), versal (4)
FPGA_FAMILY

Encoded value describing the family variant of the FPGA device(e.g., SX, GX, GT)

 0

Unknown (0), artix (1), kintex (2), virtex (3), zynq (4), versalprime (5), versalaicore (6), versalpremium (7)
SPEED_GRADE

Encoded value describing the FPGA’s speed-grade

 0

Unknown (0), -1 (10), -1L (11), -1H (12), -1HV (13), -1LV (14), -2 (20), -2L (21), -2LV (22), -2MP (23), -2LVC (24), -2LVI (25), -3 (30)
DEV_PACKAGE

Encoded value describing the device package. The package might affect high-speed interfaces

 0

Unknown (0), rf (1), fl (2), ff (3), fb (4), hc (5), fh (6), cs (7), cp (8), ft (9), fg (10), sb (11), rb (12), rs (13), cl (14), sf (15), ba (16), fa (17), fs (18), fi (19), vs (20), ls (21)
DDS_DISABLE

Dds Disable.

 0

DDS_TYPE

Dds Type.

 1

DDS_CORDIC_DW

Dds Cordic Dw.

 16

DDS_CORDIC_PHASE_DW

Dds Cordic Phase Dw.

 16

Interface

Physical Port

Logical Port

Direction

Dependency
s_axi_awaddr AWADDR

in [15:0]

s_axi_awprot AWPROT

in [2:0]

s_axi_awvalid AWVALID

in

s_axi_awready AWREADY

out

s_axi_wdata WDATA

in [31:0]

s_axi_wstrb WSTRB

in [3:0]

s_axi_wvalid WVALID

in

s_axi_wready WREADY

out

s_axi_bresp BRESP

out [1:0]

s_axi_bvalid BVALID

out

s_axi_bready BREADY

in

s_axi_araddr ARADDR

in [15:0]

s_axi_arprot ARPROT

in [2:0]

s_axi_arvalid ARVALID

in

s_axi_arready ARREADY

out

s_axi_rdata RDATA

out [31:0]

s_axi_rresp RRESP

out [1:0]

s_axi_rvalid RVALID

out

s_axi_rready RREADY

in

Physical Port

Logical Port

Direction

Dependency
s_axi_aclk CLK

in

Physical Port

Logical Port

Direction

Dependency
s_axi_aresetn RST

in

Physical Port

Logical Port

Direction

Dependency
dac_clk CLK

in

Physical Port

Direction

Dependency

Description
dma_data

in [31:0]

Data from the DMAC when input source is set to DMA_DATA.
valid_in_dma

in

Valid from the DMAC.
valid_in_dma_sec

in

Valid from a secondary DMAC if synchronization is needed.
dac_data_ready

out

Data ready signal for the DMAC.
data_in_a

in [15:0]

Data for channel 1 when input source is set to ADC_DATA.
data_in_b

in [15:0]

Data for channel 2 when input source is set to ADC_DATA.
valid_in_a

in

Valid for channel 1.
valid_in_b

in

Valid for channel 2.
dac_sclk

out

Serial clock.
dac_csn

out

Serial chip select.
sdio_i

in [3:0]

Serial data in from the DAC.
sdio_o

out [3:0]

Serial data out to the DAC.
sdio_t

out

I/O buffer control signal.
external_sync

in

External synchronization flag from another axi_ad3552r IP.
sync_ext_device

out

Start_sync external device to another axi_ad3552r IP.

Detailed Architecture

AXI AD3552R detailed architecture

Detailed Description

The top module instantiates:

  • The axi_ad3552r interface module

  • The axi_ad3552r core module

  • The AXI handling interface

The axi_ad3552r_if has the state machine that controls the quad SPI interface. The axi_ad3552r_core module instantiates 2 axi_ad3552r channel modules.

Register Map

For the AXI_AD3552R control used registers from DAC Common are:

DWORD

BYTE

Reg Name

Description

BITS

Field Name

Type

Default Value

Description
0x11 0x44 CNTRL_1

DAC Interface Control & Status

[1] EXT_SYNC_ARM RW 0x0

Setting this bit will arm the trigger mechanism sensitive to an external sync signal. Once the external sync signal goes high it synchronizes channels within a DAC, and across multiple instances. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears.
0x12 0x48 CNTRL_2

DAC Interface Control & Status

[16] SDR_DDR_N RW 0x0

Interface type (1 represents SDR, 0 represents DDR)

[14] SYMB_8_16B RW 0x0

Select number of bits for symbol format mode (1 represents 8b, 0 represents 16b)
0x21 0x84 DAC_CUSTOM_WR

DAC Write Configuration Data

[23:0] DATA_WRITE RW 0x000000

Configuration data for the AD3552R device registers. 8/16 LSB are used depending on the 8b/16b configuration.
0x22 0x88 UI_STATUS

User Interface Status

[4] IF_BUSY RO 0x0

Interface busy. If set, indicates that the data interface is busy.
0x23 0x8c DAC_CUSTOM_CTRL

DAC Control Configuration Data

[31:24] ADDRESS RW 0x00

Register address when the AD3552R is configured or stream start address when the FSM is in stream state.

[1] STREAM RW 0x0

Setting this bit will trigger a stream transfer based on the SDR/DDR configuration and address.

[0] TRANSFER_DATA RW 0x0

Setting this bit will trigger a single transfer based on the SDR/DDR, 8b/16b configuration, address, and data_write.

Access Type

Name

Description

RW

Read-write

Reads will return the current register value. Writes will change the current register value.

For the AXI_AD3552R control used registers from DAC Channel are:

DWORD

BYTE

Reg Name

Description

BITS

Field Name

Type

Default Value

Description
0x100 0x400 CHAN_CNTRL0_7

DAC Channel Control & Status (channel - 0)

[3:0] DAC_DDS_SEL RW 0x0

Select internal data sources (available only if the DAC supports it).

  • 0x00: internal tone (DDS)

  • 0x01: pattern (SED)

  • 0x02: input data (DMA)

  • 0x03: 0x00

  • 0x04: inverted pn7

  • 0x05: inverted pn15

  • 0x06: pn7 (standard O.150)

  • 0x07: pn15 (standard O.150)

  • 0x08: loopback data (ADC)

  • 0x09: pnX (Device specific e.g. ad9361)

  • 0x0A: Nibble ramp (Device specific e.g. adrv9001)

  • 0x0B: 16 bit ramp (Device specific e.g. adrv9001)
0x116 0x458 CHAN_CNTRL1_7

DAC Channel Control & Status (channel - 1)

[3:0] DAC_DDS_SEL RW 0x0

Select internal data sources (available only if the DAC supports it).

  • 0x00: internal tone (DDS)

  • 0x01: pattern (SED)

  • 0x02: input data (DMA)

  • 0x03: 0x00

  • 0x04: inverted pn7

  • 0x05: inverted pn15

  • 0x06: pn7 (standard O.150)

  • 0x07: pn15 (standard O.150)

  • 0x08: loopback data (ADC)

  • 0x09: pnX (Device specific e.g. ad9361)

  • 0x0A: Nibble ramp (Device specific e.g. adrv9001)

  • 0x0B: 16 bit ramp (Device specific e.g. adrv9001)

Access Type

Name

Description

RW

Read-write

Reads will return the current register value. Writes will change the current register value.

For reference, all the register map templates are:

DWORD

BYTE

Reg Name

Description

BITS

Field Name

Type

Default Value

Description
0x0 0x0 VERSION

Version and Scratch Registers

[31:0] VERSION RO 0x00000000

Version number. Unique to all cores.
0x1 0x4 ID

Version and Scratch Registers

[31:0] ID RO 0x00000000

Instance identifier number.
0x2 0x8 SCRATCH

Version and Scratch Registers

[31:0] SCRATCH RW 0x00000000

Scratch register.
0x3 0xc CONFIG

Version and Scratch Registers

[0] IQCORRECTION_DISABLE RO 0x0

If set, indicates that the IQ Correction module was not implemented. (as a result of a configuration of the IP instance)

[1] DCFILTER_DISABLE RO 0x0

If set, indicates that the DC Filter module was not implemented. (as a result of a configuration of the IP instance)

[2] DATAFORMAT_DISABLE RO 0x0

If set, indicates that the Data Format module was not implemented. (as a result of a configuration of the IP instance)

[3] USERPORTS_DISABLE RO 0x0

If set, indicates that the logic related to the User Data Format (e.g. decimation) was not implemented. (as a result of a configuration of the IP instance)

[4] MODE_1R1T RO 0x0

If set, indicates that the core was implemented in 1 channel mode. (e.g. refer to AD9361 data sheet)

[5] DELAY_CONTROL_DISABLE RO 0x0

If set, indicates that the delay control is disabled for this IP. (as a result of a configuration of the IP instance)

[6] DDS_DISABLE RO 0x0

If set, indicates that the DDS is disabled for this IP. (as a result of a configuration of the IP instance)

[7] CMOS_OR_LVDS_N RO 0x0

CMOS or LVDS mode is used for the interface. (as a result of a configuration of the IP instance)

[8] PPS_RECEIVER_ENABLE RO 0x0

If set, indicates the PPS receiver is enabled. (as a result of a configuration of the IP instance)

[9] SCALECORRECTION_ONLY RO 0x0

If set, indicates that the IQ Correction module implements only scale correction. IQ correction must be enabled. (as a result of a configuration of the IP instance)

[12] EXT_SYNC RO 0x0

If set the transport layer cores (ADC/DAC) have implemented the support for external synchronization signal.

[13] RD_RAW_DATA RO 0x0

If set, the ADC has the capability to read raw data in register CHAN_RAW_DATA from adc_channel.
0x4 0x10 PPS_IRQ_MASK

PPS Interrupt mask

[0] PPS_IRQ_MASK RW 0x1

Mask bit for the 1PPS receiver interrupt
0x7 0x1c FPGA_INFO

FPGA device information library/scripts/adi_intel_device_info_enc.tcl (Intel encoded values) library/scripts/adi_xilinx_device_info_enc.tcl (Xilinx encoded values)

[31:24] FPGA_TECHNOLOGY RO 0x00

Encoded value describing the technology/generation of the FPGA device (arria 10/7series)

[23:16] FPGA_FAMILY RO 0x00

Encoded value describing the family variant of the FPGA device(e.g., SX, GX, GT or zynq, kintex, virtex)

[15:8] SPEED_GRADE RO 0x00

Encoded value describing the FPGA’s speed-grade

[7:0] DEV_PACKAGE RO 0x00

Encoded value describing the device package. The package might affect high-speed interfaces

DWORD

BYTE

Reg Name

Description

BITS

Field Name

Type

Default Value

Description
0x10 0x40 RSTN

DAC Interface Control & Status

[2] CE_N RW 0x0

Clock enable, default is enabled(0x0). An inverse version of the signal is exported out of the module to control clock enables

[1] MMCM_RSTN RW 0x0

MMCM reset only (required for DRP access). Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.

[0] RSTN RW 0x0

Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.
0x11 0x44 CNTRL_1

DAC Interface Control & Status

[0] SYNC RW 0x0

Setting this bit synchronizes channels within a DAC, and across multiple instances. This bit self clears.

[1] EXT_SYNC_ARM RW 0x0

Setting this bit will arm the trigger mechanism sensitive to an external sync signal. Once the external sync signal goes high it synchronizes channels within a DAC, and across multiple instances. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears.

[2] EXT_SYNC_DISARM RW 0x0

Setting this bit will disarm the trigger mechanism sensitive to an external sync signal. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears.

[8] MANUAL_SYNC_REQUEST RW 0x0

Setting this bit will issue an external sync event if it is hooked up inside the fabric. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears.
0x12 0x48 CNTRL_2

DAC Interface Control & Status

[16] SDR_DDR_N RW 0x0

Interface type (1 represents SDR, 0 represents DDR)

[15] SYMB_OP RW 0x0

Select data symbol format mode (0x1)

[14] SYMB_8_16B RW 0x0

Select number of bits for symbol format mode (1 represents 8b, 0 represents 16b)

[12:8] NUM_LANES RW 0x00

Number of active lanes (1 : CSSI 1-lane, LSSI 1-lane, 2 : LSSI 2-lane, 4 : CSSI 4-lane)

[7] PAR_TYPE RW 0x0

Select parity even (0x0) or odd (0x1).

[6] PAR_ENB RW 0x0

Select parity (0x1) or frame (0x0) mode.

[5] R1_MODE RW 0x0

Select number of RF channels 1 (0x1) or 2 (0x0).

[4] DATA_FORMAT RW 0x0

Select data format 2’s complement (0x0) or offset binary (0x1). NOT-APPLICABLE if DAC_DP_DISABLE is set (0x1).

[3:0] RESERVED NA 0x0

Reserved
0x13 0x4c RATECNTRL

DAC Interface Control & Status

[7:0] RATE RW 0x00

The effective dac rate (the maximum possible rate is dependent on the interface clock). The samples are generated at 1/RATE of the interface clock.
0x14 0x50 FRAME

DAC Interface Control & Status

[0] FRAME RW 0x0

The use of frame is device specific. Usually setting this bit to 1 generates a FRAME (1 DCI clock period) pulse on the interface. This bit self clears.
0x15 0x54 STATUS1

DAC Interface Control & Status

[31:0] CLK_FREQ RO 0x00000000

Interface clock frequency. This is relative to the processor clock and in many cases is 100MHz. The number is represented as unsigned 16.16 format. Assuming a 100MHz processor clock the minimum is 1.523kHz and maximum is 6.554THz. The actual interface clock is CLK_FREQ * CLK_RATIO (see below). Note that the actual sampling clock may not be the same as the interface clock- software must consider device specific implementation parameters to calculate the final sampling clock.
0x16 0x58 STATUS2

DAC Interface Control & Status

[31:0] CLK_RATIO RO 0x00000000

Interface clock ratio - as a factor actual received clock. This is implementation specific and depends on any serial to parallel conversion and interface type (ddr/sdr/qdr).
0x17 0x5c STATUS3

DAC Interface Control & Status

[0] STATUS RO 0x0

Interface status, if set indicates no errors. If not set, there are errors, software may try resetting the cores.
0x18 0x60 DAC_CLKSEL

DAC Interface Control & Status

[0] DAC_CLKSEL RW 0x0

Allows changing of the clock polarity. Note: its default value is CLK_EDGE_SEL
0x1a 0x68 SYNC_STATUS

DAC Synchronization Status register

[0] DAC_SYNC_STATUS RO 0x0

DAC synchronization status. Will be set to 1 while waiting for the external synchronization signal This bit has an effect only the EXT_SYNC synthesis parameter is set.
0x1c 0x70 DRP_CNTRL

DRP Control & Status

[28] DRP_RWN RW 0x0

DRP read (0x1) or write (0x0) select (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).

[27:16] DRP_ADDRESS RW 0x000

DRP address, designs that contain more than one DRP accessible primitives have selects based on the most significant bits (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).

[15:0] RESERVED RO 0x0000

Reserved for backwards compatibility
0x1d 0x74 DRP_STATUS

DAC Interface Control & Status

[17] DRP_LOCKED RO 0x0

If set indicates the MMCM/PLL is locked

[16] DRP_STATUS RO 0x0

If set indicates busy (access pending). The read data may not be valid if this bit is set (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).

[15:0] RESERVED RO 0x0000

Reserved for backwards compatibility
0x1e 0x78 DRP_WDATA

DAC Interface Control & Status

[15:0] DRP_WDATA RW 0x0000

DRP write data (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).
0x1f 0x7c DRP_RDATA

DAC Interface Control & Status

[15:0] DRP_RDATA RO 0x0000

DRP read data (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).
0x20 0x80 DAC_CUSTOM_RD

DAC Read Configuration Data

[31:0] DAC_CUSTOM_RD RO 0x00000000

Custom Read of the available registers.
0x21 0x84 DAC_CUSTOM_WR

DAC Write Configuration Data

[31:0] DAC_CUSTOM_WR RW 0x00000000

Custom Write of the available registers.
0x22 0x88 UI_STATUS

User Interface Status

[4] IF_BUSY RO 0x0

Interface busy. If set, indicates that the data interface is busy.

[1] UI_OVF RW1C 0x0

User Interface overflow. If set, indicates an overflow occurred during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit.

[0] UI_UNF RW1C 0x0

User Interface underflow. If set, indicates an underflow occurred during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit.
0x23 0x8c DAC_CUSTOM_CTRL

DAC Control Configuration Data

[31:0] DAC_CUSTOM_CTRL RW 0x00000000

Custom Control of the available registers.
0x28 0xa0 USR_CNTRL_1

DAC User Control & Status

[7:0] USR_CHANMAX RW 0x00

This indicates the maximum number of inputs for the channel data multiplexers. User may add different processing modules as inputs to the dac. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
0x2e 0xb8 DAC_GPIO_IN

DAC GPIO inputs

[31:0] DAC_GPIO_IN RO 0x00000000

This reads auxiliary GPI pins of the DAC core
0x2f 0xbc DAC_GPIO_OUT

DAC GPIO outputs

[31:0] DAC_GPIO_OUT RW 0x00000000

This controls auxiliary GPO pins of the DAC core NOT-APPLICABLE if GPIO_DISABLE is set (0x1).

DWORD

BYTE

Reg Name

Description

BITS

Field Name

Type

Default Value

Description
0x100 + 0x16*n 0x400 + 0x58*n CHAN_CNTRLn_1

DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.

[21:16] DDS_PHASE_DW RO 0x00

The DDS phase data width offers the HDL parameter configuration with the same name. This information is used in conjunction with CHAN_CNTRL_9 and CHAN_CNTRL_10. More info at AD Direct Digital Synthesis.

[15:0] DDS_SCALE_1 RW 0x0000

The DDS scale for tone 1. Sets the amplitude of the tone. The format is 1.1.14 fixed point (signed, integer, fractional). The DDS in general runs on 16-bits, note that if you do use both channels and set both scale to 0x4000, it is over-range. The final output is (tone_1_fullscale * scale_1) + (tone_2_fullscale * scale_2). NOT-APPLICABLE if DDS_DISABLE is set (0x1).
0x101 + 0x16*n 0x404 + 0x58*n CHAN_CNTRLn_2

DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.

[31:16] DDS_INIT_1 RW 0x0000

The DDS phase initialization for tone 1. Sets the initial phase offset of the tone. NOT-APPLICABLE if DDS_DISABLE is set (0x1).

[15:0] DDS_INCR_1 RW 0x0000

Sets the frequency of the phase accumulator. Its value can be calculated by \(INCR = (f_{out} * 2^{16}) * clkratio / f_{if}\); where f_out is the generated output frequency, and f_if is the frequency of the digital interface, and clock_ratio is the ratio between the sampling clock and the interface clock. If DDS_PHASE_DW is greater than 16(from CHAN_CNTRL_1), the phase increment for tone 1 is extended in CHAN_CNTRL_9. NOT-APPLICABLE if DDS_DISABLE is set (0x1).
0x102 + 0x16*n 0x408 + 0x58*n CHAN_CNTRLn_3

DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.

[15:0] DDS_SCALE_2 RW 0x0000

The DDS scale for tone 2. Sets the amplitude of the tone. The format is 1.1.14 fixed point (signed, integer, fractional). The DDS in general runs on 16-bits, note that if you do use both channels and set both scale to 0x4000, it is over-range. The final output is (tone_1_fullscale * scale_1) + (tone_2_fullscale * scale_2). NOT-APPLICABLE if DDS_DISABLE is set (0x1).
0x103 + 0x16*n 0x40c + 0x58*n CHAN_CNTRLn_4

DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.

[31:16] DDS_INIT_2 RW 0x0000

The DDS phase initialization for tone 2. Sets the initial phase offset of the tone. If DDS_PHASE_DW is greater than 16(from CHAN_CNTRL_1), the phase init for tone 2 is extended in CHAN_CNTRL_10. NOT-APPLICABLE if DDS_DISABLE is set (0x1).

[15:0] DDS_INCR_2 RW 0x0000

Sets the frequency of the phase accumulator. Its value can be calculated by \(INCR = (f_{out} * 2^{16}) * clkratio / f_{if}\); where f_out is the generated output frequency, and f_if is the frequency of the digital interface, and clock_ratio is the ratio between the sampling clock and the interface clock. If DDS_PHASE_DW is greater than 16(from CHAN_CNTRL_1), the phase increment for tone 2 is extended in CHAN_CNTRL_10. NOT-APPLICABLE if DDS_DISABLE is set (0x1).
0x104 + 0x16*n 0x410 + 0x58*n CHAN_CNTRLn_5

DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.

[31:16] DDS_PATT_2 RW 0x0000

The DDS data pattern for this channel.

[15:0] DDS_PATT_1 RW 0x0000

The DDS data pattern for this channel.
0x105 + 0x16*n 0x414 + 0x58*n CHAN_CNTRLn_6

DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.

[2] IQCOR_ENB RW 0x0

if set, enables IQ correction. NOT-APPLICABLE if DAC_DP_DISABLE is set (0x1).

[1] DAC_LB_OWR RW 0x0

If set, forces DAC_DDS_SEL to 0x8, loopback If DAC_LB_OWR and DAC_PN_OWR are both set, they are ignored

[0] DAC_PN_OWR RW 0x0

IF set, forces DAC_DDS_SEL to 0x09, device specific pnX If DAC_LB_OWR and DAC_PN_OWR are both set, they are ignored
0x106 + 0x16*n 0x418 + 0x58*n CHAN_CNTRLn_7

DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.

[3:0] DAC_DDS_SEL RW 0x0

Select internal data sources (available only if the DAC supports it).

  • 0x00: internal tone (DDS)

  • 0x01: pattern (SED)

  • 0x02: input data (DMA)

  • 0x03: 0x00

  • 0x04: inverted pn7

  • 0x05: inverted pn15

  • 0x06: pn7 (standard O.150)

  • 0x07: pn15 (standard O.150)

  • 0x08: loopback data (ADC)

  • 0x09: pnX (Device specific e.g. ad9361)

  • 0x0A: Nibble ramp (Device specific e.g. adrv9001)

  • 0x0B: 16 bit ramp (Device specific e.g. adrv9001)
0x107 + 0x16*n 0x41c + 0x58*n CHAN_CNTRLn_8

DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.

[31:16] IQCOR_COEFF_1 RW 0x0000

IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the scale value and the format is 1.1.14 (sign, integer and fractional bits). If matrix multiplication is used, this is the channel I coefficient and the format is 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).

[15:0] IQCOR_COEFF_2 RW 0x0000

IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the offset value and the format is 2’s complement. If matrix multiplication is used, this is the channel Q coefficient and the format is 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).
0x108 + 0x16*n 0x420 + 0x58*n USR_CNTRLn_3

DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.

[25] USR_DATATYPE_BE RW 0x0

The user data type format- if set, indicates big endian (default is little endian). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

[24] USR_DATATYPE_SIGNED RW 0x0

The user data type format- if set, indicates signed (2’s complement) data (default is unsigned). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

[23:16] USR_DATATYPE_SHIFT RW 0x00

The user data type format- the amount of right shift for actual samples within the total number of bits. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

[15:8] USR_DATATYPE_TOTAL_BITS RW 0x00

The user data type format- number of total bits used for a sample. The total number of bits must be an integer multiple of 8 (byte aligned). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

[7:0] USR_DATATYPE_BITS RW 0x00

The user data type format- number of bits in a sample. This indicates the actual sample data bits. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
0x109 + 0x16*n 0x424 + 0x58*n USR_CNTRLn_4

DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.

[31:16] USR_INTERPOLATION_M RW 0x0000

This holds the user interpolation M value of the channel that is currently being selected on the multiplexer above. The total interpolation factor is of the form M/N. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

[15:0] USR_INTERPOLATION_N RW 0x0000

This holds the user interpolation N value of the channel that is currently being selected on the multiplexer above. The total interpolation factor is of the form M/N. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
0x10a + 0x16*n 0x428 + 0x58*n USR_CNTRLn_5

DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.

[0] DAC_IQ_MODE RW 0x0

Enable complex mode. In this mode the driven data to the DAC must be a sequence of I and Q sample pairs.

[1] DAC_IQ_SWAP RW 0x0

Allows IQ swapping in complex mode. Only takes effect if complex mode is enabled.
0x10b + 0x16*n 0x42c + 0x58*n CHAN_CNTRLn_9

DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.

[31:16] DDS_INIT_1_EXTENDED RW 0x0000

The extended DDS phase initialization for tone 1. Sets the initial phase offset of the tone. The extended init(phase) value should be calculated according to DDS_PHASE_DW value from CHAN_CNTRL_1 NOT-APPLICABLE if DDS_DISABLE is set (0x1).

[15:0] DDS_INCR_1_EXTENDED RW 0x0000

Sets the frequency of tone 1’s phase accumulator. Its value can be calculated by \(INCR = (f_{out} * 2^{phaseDW}) * clkratio / f_{if}\); Where f_out is the generated output frequency, DDS_PHASE_DW value can be found in CHAN_CNTRL_1 in case DDS_PHASE_DW is not 16, f_if is the frequency of the digital interface, and clock_ratio is the ratio between the sampling clock and the interface clock. NOT-APPLICABLE if DDS_DISABLE is set (0x1).
0x10c + 0x16*n 0x430 + 0x58*n CHAN_CNTRLn_10

DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.

[31:16] DDS_INIT_2_EXTENDED RW 0x0000

The extended DDS phase initialization for tone 2. Sets the initial phase offset of the tone. The extended init(phase) value should be calculated according to DDS_PHASE_DW value from CHAN_CNTRL_2 NOT-APPLICABLE if DDS_DISABLE is set (0x1).

[15:0] DDS_INCR_2_EXTENDED RW 0x0000

Sets the frequency of tone 2’s phase accumulator. Its value can be calculated by \(INCR = (f_{out} * 2^{phaseDW}) * clkratio / f_{if}\); Where f_out is the generated output frequency, DDS_PHASE_DW value can be found in CHAN_CNTRL_2 in case DDS_PHASE_DW is not 16, f_if is the frequency of the digital interface, and clock_ratio is the ratio between the sampling clock and the interface clock. NOT-APPLICABLE if DDS_DISABLE is set (0x1).

Design Guidelines

The control of the chip is done through the AXI_AD3552R IP.

The DAC interface must be connected to an IO buffer.

The example design uses a DMA to move the data from the memory to the CHIP quad SPI interface.

If the data needs to be processed in HDL before moving to DAC’s output, it can be done at the input of the IP (at the system level) or inside the axi_ad3552r_if interface module (at the IP level).

The example design uses a processor to program all the registers. If no processor is available in your system, you can create your IP starting from the interface module.

Software Support

References