Util Sigma Delta SPI#

ADCs from the ADI Sigma-Delta converter family use a low-level communication protocol that multiplexes the SPI bus MISO signal and the data ready interrupt signal over the same physical wire (DOUT/RDY).

The Sigma-Delta SPI Util peripheral can be used to de-multiplex these signals inside a FPGA.

Files#

Name	Description
library/util_sigma_delta_spi/util_sigma_delta_spi.v	Verilog source for the peripheral
library/util_sigma_delta_spi/util_sigma_delta_spi_ip.tcl	Tcl script to generate the Vivado IP Integrator project for the peripheral

Configuration Parameters#

Name	Description	Default Value
`NUM_OF_CS`	Num Of Cs.	`1`
`CS_PIN`	Cs Pin.	`0`
`IDLE_TIMEOUT`	Idle Timeout.	`63`

Interface#

m_spi

Physical Port	Logical Port	Direction
`m_sclk`	`SCLK`	out
`m_sdi`	`SDI`	in
`m_sdo`	`SDO`	out
`m_sdo_t`	`SDO_T`	out
`m_cs`	`CS`	out [0:0]

s_spi

Physical Port	Logical Port	Direction
`s_sclk`	`SCLK`	in
`s_sdi`	`SDI`	out
`s_sdo`	`SDO`	in
`s_sdo_t`	`SDO_T`	in
`s_cs`	`CS`	in [0:0]

Ports

Physical Port	Direction	Description
`clk`	in	Bus `m_spi_s_spi` is synchronous to this clock domain.
`resetn`	in	Bus `m_spi_s_spi` is synchronous to this reset signal.
`spi_active`	in
`data_ready`	out

Detailed Description#

The Sigma-Delta SPI Util peripheral monitors the SPI bus that is connected to the s_spi interface for the converter’s data ready condition.

The m_spi interface is directly connected to the s_spi interface. In a typical configuration, the s_spi interface is connected to a SPI controller and the m_spi interface is connected to external SPI bus pins.

The data_ready signal is high-level active and will be asserted as long as the data ready condition is detected.

For example, it can be connected to an interrupt controller to start an interrupt service routine that will read the converted data sample from the ADC, or it can be connected to a HDL block, like the SPI Engine Offload block that will generate a SPI transaction to read the converted signal.

The data ready condition is only detected if the chip-select signal (which is connected to the converter) is asserted and the spi_active signal is de-asserted and both signals have been in that state for at least IDLE_TIMEOUT clock cycles.

The timeout is used to avoid spurious signal detection and the IDLE_TIMEOUT parameter should be configured so that the period it takes to complete IDLE_TIMEOUT clock cycles with the clk clock, is larger than the “CS falling edge to DOUT/RDY active time” and “SCLK inactive edge to DOUT/RDY high/low” as specified in the data sheet for the converter.

References#

HDL IP core at library/util_sigma_delta_spi