CN0579 HDL project

Overview

The CN0579 is a 4-channel, high resolution, wide bandwidth, high dynamic range, integrated electronics piezoelectric (IEPE)-compatible interface data acquisition (DAQ) system that interfaces with IC piezoelectric (ICP®)/IEPE sensors. The solution provides flexible sensor interfacing to either piezoelectric or micro-electromechanical systems (MEMS) sensor with measurement capabilities that extend the frequency response to DC.

The design provides four channels of full bandwidth, synchronized vibration data to the processor, where data analysis can be done locally or on a remote host over Ethernet via standard IIO framework. Large buffers of continuous data can be streamed and analyzed using standard fast Fourier transform (FFT) techniques for system characterization and machine learning algorithms.

Supported boards

Supported devices

Supported carriers

Evaluation board

Carrier

FMC slot

CN0579

Cora Z7S

Arduino headers

DE10-Nano

Arduino headers

Block design

Block diagram

The data path and clock domains are depicted in the below diagram:

CN0579 block diagram

Clock scheme

CN0579 clock scheme

CPU/Memory interconnects addresses

The addresses are dependent on the architecture of the FPGA, having an offset added to the base address from HDL (see more at CPU/Memory interconnects addresses).

Instance

Zynq

Cyclone V

axi_ad77684_adc

0x44A0_0000

0x0002_8000

cn0579_dma

0x44A3_0000

0x0003_0000

axi_iic_dac*

0x44A4_0000

Legend

* instantiated only for Cora Z7S

I2C connections

I2C type

I2C manager instance

Alias

Address

I2C subordinate

PL*

axi_iic

axi_iic_dac

0x0C

AD5696R

PS**

I2C1

0x0C

AD5696R

Legend

  • * only for Cora Z7S

  • ** only for DE10-Nano

SPI connections

SPI type

SPI manager instance

SPI subordinate

CS

PS*

SPI 0

AD7786-4

0

PL**

SYS_SPI

AD7786-4

0

Legend

  • * only for Cora Z7S

  • ** only for DE10-Nano

GPIOs

GPIO signal

Direction

HDL GPIO EMIO

Software GPIO

Software GPIO

(from FPGA view)

Zynq-7000

Cyclone V

RESET_N

OUT

32

86

0

Interrupts

Below are the Programmable Logic interrupts used in this project.

Instance name

HDL

Linux Zynq

Actual Zynq

Linux Cyclone V

Actual Cyclone V

cn0579_dma*

12

56

88

axi_iic_ard*

11

55

87

cn0579_dma**

5

45

77

Legend

  • * only for Cora Z7S

  • ** only for DE10-Nano

Building the HDL project

The design is built upon ADI’s generic HDL reference design framework. ADI distributes the bit/elf files of these projects as part of the ADI Kuiper Linux. If you want to build the sources, ADI makes them available on the HDL repository. To get the source you must clone the HDL repository, and then build the project as follows:

Linux/Cygwin/WSL

Building the CoraZ7S project:

~$
cd hdl/projects/cn0579/coraz7s
~/hdl/projects/cn0579/coraz7s$
make

Building the DE-10Nano project:

~$
cd hdl/projects/cn0579/de10nano
~/hdl/projects/cn0579/de10nano$
make

A more comprehensive build guide can be found in the Build an HDL project user guide.

Resources

More information

Support

Analog Devices, Inc. will provide limited online support for anyone using the reference design with ADI components via the EngineerZone FPGA reference designs forum.

For questions regarding the ADI Linux device drivers, device trees, etc. from our Linux GitHub repository, the team will offer support on the EngineerZone Linux software drivers forum.

For questions concerning the ADI No-OS drivers, from our No-OS GitHub repository, the team will offer support on the EngineerZone microcontroller No-OS drivers forum.

It should be noted, that the older the tools’ versions and release branches are, the lower the chances to receive support from ADI engineers.