AXI ADXCVR

The AXI ADXCVR utility IP core is used to control and configure the highspeed transceivers. There are separate AXI ADXCVR cores for Intel and AMD Xilinx designs, due to the small differences between the AMD Xilinx’s and Intel’s transceivers architecture. For the AMD Xilinx architecture, the transceivers are instantiated in UTIL_ADXCVR.

Features

  • Supports Intel and AMD Xilinx devices.

  • Software can access the core’s registers through an AXI4 Lite Memory Mapped interface.

  • Link reset and monitor for Intel and AMD Xilinx.

  • Reconfiguration interface control with broadcast capability for AMD Xilinx.

  • Access to the Statistical eye scan interface of the PHY (AMD Xilinx).

  • Supports up to 16 transceiver lanes per link (AMD Xilinx).

Intel Devices

For Intel devices, the ADI JESD204 IP is using the AXI ADXCVR core, which can be accessed by the link_management interface. It provides a global reset signal for the JESD204B framework. Resets the XCVR reset controller IP, the link PLL reset controller, the PHY itself, and also the link layer of the stack. Besides the reset generation, monitors the PLLs and the PHY state.

Parameters

Name

Description

Default Value

Choices/Range
ID

Instance identification number, if more than one instance is used.

 0

NUM_OF_LANES

The number of lanes (primitives) used in this link.

 8

XCVR_TYPE

Refers to the transceiver speed grade 0-9.

 0

Unknown (0), GTPE2_NOT_SUPPORTED (1), GTXE2 (2), GTHE2_NOT_SUPPORTED (3), GTZE2_NOT_SUPPORTED (4), GTHE3 (5), GTYE3_NOT_SUPPORTED (6), GTRE4_NOT_SUPPORTED (7), GTHE4 (8), GTYE4 (9), GTME4_NOT_SUPPORTED (10)
LINK_MODE

Link Layer mode.

 1

64B66B (2), 8B10B (1)
FPGA_TECHNOLOGY

Encoded value describing the technology/generation of the FPGA device (e.g. Cyclone V, Arria 10, Stratix 10).

 0

Unknown (0), 7series (1), ultrascale (2), ultrascale+ (3), versal (4)
FPGA_FAMILY

Encoded value describing the family variant of the FPGA device (e.g. SX, GX, GT).

 0

Unknown (0), artix (1), kintex (2), virtex (3), zynq (4), versalprime (5), versalaicore (6), versalpremium (7)
SPEED_GRADE

Encoded value describing the FPGA’s speed-grade.

 0

Unknown (0), -1 (10), -1L (11), -1H (12), -1HV (13), -1LV (14), -2 (20), -2L (21), -2LV (22), -2MP (23), -2LVC (24), -2LVI (25), -3 (30)
DEV_PACKAGE

Encoded value describing the device package. The package might affect high-speed interfaces.

 0

Unknown (0), rf (1), fl (2), ff (3), fb (4), hc (5), fh (6), cs (7), cp (8), ft (9), fg (10), sb (11), rb (12), rs (13), cl (14), sf (15), ba (16), fa (17), fs (18), fi (19), vs (20), ls (21)
FPGA_VOLTAGE

Contains the value(0-5000 mV) at wich the FPGA device supplied.

 0

From 0 to 5000.
TX_OR_RX_N

If set (0x1), configures the link in transmit mode, otherwise receive.

 0

QPLL_ENABLE

Qpll Enable.

 1

LPM_OR_DFE_N

Lpm Or Dfe N.

 1

RATE

Rate.

 'b000

TX_DIFFCTRL

Tx Diffctrl.

 'b01000

TX_POSTCURSOR

Tx Postcursor.

 'b00000

TX_PRECURSOR

Tx Precursor.

 'b00000

SYS_CLK_SEL

Sys Clk Sel.

 'b11

OUT_CLK_SEL

Out Clk Sel.

 'b100

Interfaces

Physical Port

Logical Port

Direction

Dependency
s_axi_awaddr AWADDR

in [15:0]

s_axi_awprot AWPROT

in [2:0]

s_axi_awvalid AWVALID

in

s_axi_awready AWREADY

out

s_axi_wdata WDATA

in [31:0]

s_axi_wstrb WSTRB

in [3:0]

s_axi_wvalid WVALID

in

s_axi_wready WREADY

out

s_axi_bresp BRESP

out [1:0]

s_axi_bvalid BVALID

out

s_axi_bready BREADY

in

s_axi_araddr ARADDR

in [15:0]

s_axi_arprot ARPROT

in [2:0]

s_axi_arvalid ARVALID

in

s_axi_arready ARREADY

out

s_axi_rdata RDATA

out [31:0]

s_axi_rresp RRESP

out [1:0]

s_axi_rvalid RVALID

out

s_axi_rready RREADY

in

Physical Port

Logical Port

Direction

Dependency
s_axi_aclk CLK

in

Physical Port

Logical Port

Direction

Dependency
s_axi_aresetn RST

in

Physical Port

Logical Port

Direction

Dependency
m_axi_awaddr AWADDR

out [31:0]

m_axi_awprot AWPROT

out [2:0]

m_axi_awvalid AWVALID

out

m_axi_awready AWREADY

in

m_axi_wdata WDATA

out [31:0]

m_axi_wstrb WSTRB

out [3:0]

m_axi_wvalid WVALID

out

m_axi_wready WREADY

in

m_axi_bresp BRESP

in [1:0]

m_axi_bvalid BVALID

in

m_axi_bready BREADY

out

m_axi_araddr ARADDR

out [31:0]

m_axi_arprot ARPROT

out [2:0]

m_axi_arvalid ARVALID

out

m_axi_arready ARREADY

in

m_axi_rdata RDATA

in [31:0]

m_axi_rresp RRESP

in [1:0]

m_axi_rvalid RVALID

in

m_axi_rready RREADY

out

Physical Port

Logical Port

Direction

Dependency
up_pll_rst RST

out

Physical Port

Logical Port

Direction

Dependency
* ready

in

Physical Port

Logical Port

Direction

Dependency
* ready

in

Physical Port

Logical Port

Direction

Dependency
* ready

in

Physical Port

Direction

Dependency

Description
up_status

out

Register Map

DWORD

BYTE

Reg Name

Description

BITS

Field Name

Type

Default Value

Description
0x0 0x0 VERSION

Version Register

[31:0] VERSION RO

Version number.
0x1 0x4 ID

Instance Identification Register

[31:0] ID RO

Instance identifier number.
0x2 0x8 SCRATCH

Scratch (GP R/W) Register

[31:0] SCRATCH RW

Scratch register.
0x4 0x10 RESETN

Reset Control Register

[0] RESETN RW

If clear, link is held in reset, set this bit to 0x1 to activate link. Note that the reference clock must be active before setting this bit.
0x5 0x14 STATUS

Status Reporting Register

[0] STATUS RO

After setting the RESETN bit above, wait for this bit to set. If set, indicates successful link activation.
0x6 0x18 STATUS_32

Status Reporting Register

[31:NUM_OF_LANES+1] RESERVED RO

0

[NUM_OF_LANES] UP_PLL_LOCKED RO

After setting the RESETN bit above, wait for this bit be to set.

[NUM_OF_LANES-1:0] CHANNEL_N_READY RO

After setting the RESETN bit above, wait for this registers to be set.
0x7 0x1c FPGA_INFO

FPGA device information Intel Encoded Values

[31:24] FPGA_TECHNOLOGY RO

Encoded value describing the technology/generation of the FPGA device (e.g., cyclone V, arria 10, stratix 10)

[23:16] FPGA_FAMILY RO

Encoded value describing the family variant of the FPGA device(e.g., SX, GX, GT or zynq, kintex, virtex)

[15:8] SPEED_GRADE RO

Encoded value describing the FPGA’s speed-grade

[7:0] DEV_PACKAGE RO

Encoded value describing the device package. The package might affect high-speed interfaces
0x9 0x24 GENERIC_INFO

Physical layer info

[31:28] RESERVED RO

0

[27:24] XCVR_TYPE RO

Refers to the transceiver speed grade 0-9.

[23:12] RESERVED RO

0

[11:9] RESERVED RO

0

[8] TX_OR_RX_N RO

Transceiver type (transmit or receive)

[7:0] NUM_OF_LANES RO

Physical layer number of lanes.
0x50 0x140 FPGA_VOLTAGE

FPGA device voltage information

[15:0] FPGA_VOLTAGE RO

The voltage of the FPGA device in mv

Software Guidelines

When the board powers up, both ATX and fPLL’s must have a stable reference clock in order to lock automatically. If this requirement can not be respected by the system (e.g. the reference clocks are generated by a device that requires software configuration, through an interface implemented in FPGA), the software needs to reconfigure both PLLs, and just after that resets the transceivers.

AMD Xilinx Devices

In AMD Xilinx Devices, the core configures itself to be interfaced with the GT variant supported by the UTIL_ADXCVR core. All the transceiver primitives are configured and programmed identically.

Parameters

Name

Description

Default Value

Choices/Range
ID

Instance identification number, if more than one instance is used

 0

NUM_OF_LANES

The number of lanes (primitives) used in this link

 8

XCVR_TYPE

Define the current GT type, GTXE2(2), GTHE3(5), GTHE4(7)

 0

Unknown (0), GTPE2_NOT_SUPPORTED (1), GTXE2 (2), GTHE2_NOT_SUPPORTED (3), GTZE2_NOT_SUPPORTED (4), GTHE3 (5), GTYE3_NOT_SUPPORTED (6), GTRE4_NOT_SUPPORTED (7), GTHE4 (8), GTYE4 (9), GTME4_NOT_SUPPORTED (10)
LINK_MODE

Link Layer mode.

 1

64B66B (2), 8B10B (1)
FPGA_TECHNOLOGY

Encoded value describing the technology/generation of the FPGA device (7series/ultrascale)

 0

Unknown (0), 7series (1), ultrascale (2), ultrascale+ (3), versal (4)
FPGA_FAMILY

Encoded value describing the family variant of the FPGA device(e.g., zynq, kintex, virtex)

 0

Unknown (0), artix (1), kintex (2), virtex (3), zynq (4), versalprime (5), versalaicore (6), versalpremium (7)
SPEED_GRADE

Encoded value describing the FPGA’s speed-grade

 0

Unknown (0), -1 (10), -1L (11), -1H (12), -1HV (13), -1LV (14), -2 (20), -2L (21), -2LV (22), -2MP (23), -2LVC (24), -2LVI (25), -3 (30)
DEV_PACKAGE

Encoded value describing the device package. The package might affect high-speed interfaces

 0

Unknown (0), rf (1), fl (2), ff (3), fb (4), hc (5), fh (6), cs (7), cp (8), ft (9), fg (10), sb (11), rb (12), rs (13), cl (14), sf (15), ba (16), fa (17), fs (18), fi (19), vs (20), ls (21)
FPGA_VOLTAGE

Contains the value(0-5000 mV) at wich the FPGA device supplied

 0

From 0 to 5000.
TX_OR_RX_N

If set (0x1), configures the link in transmit mode, otherwise receive

 0

QPLL_ENABLE

If set (0x1), configures the link to use QPLL on QUAD basis. If multiple links are sharing the same transceiver, only one of them may enable the QPLL.

 1

LPM_OR_DFE_N

Chosing between LPM or DFE of modes for the RX Equalizer

 1

RATE

Defines the initial values for Transceiver Control Register (CONTROL 0x0008)

 'b000

TX_DIFFCTRL

Driver Swing Control(TX Configurable Driver)

 'b01000

TX_POSTCURSOR

Transmitter post-cursor TX pre-emphasis control

 'b00000

TX_PRECURSOR

Transmitter pre-cursor TX pre-emphasis control

 'b00000

SYS_CLK_SEL

Selects the PLL reference clock source to drive the RXOUTCLK Table 1

 'b11

OUT_CLK_SEL

select the transceiver reference clock as the source of TXOUTCLK Table 2

 'b100

Interfaces

Physical Port

Logical Port

Direction

Dependency
s_axi_awaddr AWADDR

in [15:0]

s_axi_awprot AWPROT

in [2:0]

s_axi_awvalid AWVALID

in

s_axi_awready AWREADY

out

s_axi_wdata WDATA

in [31:0]

s_axi_wstrb WSTRB

in [3:0]

s_axi_wvalid WVALID

in

s_axi_wready WREADY

out

s_axi_bresp BRESP

out [1:0]

s_axi_bvalid BVALID

out

s_axi_bready BREADY

in

s_axi_araddr ARADDR

in [15:0]

s_axi_arprot ARPROT

in [2:0]

s_axi_arvalid ARVALID

in

s_axi_arready ARREADY

out

s_axi_rdata RDATA

out [31:0]

s_axi_rresp RRESP

out [1:0]

s_axi_rvalid RVALID

out

s_axi_rready RREADY

in

Physical Port

Logical Port

Direction

Dependency
s_axi_aclk CLK

in

Physical Port

Logical Port

Direction

Dependency
s_axi_aresetn RST

in

Physical Port

Logical Port

Direction

Dependency
m_axi_awaddr AWADDR

out [31:0]

m_axi_awprot AWPROT

out [2:0]

m_axi_awvalid AWVALID

out

m_axi_awready AWREADY

in

m_axi_wdata WDATA

out [31:0]

m_axi_wstrb WSTRB

out [3:0]

m_axi_wvalid WVALID

out

m_axi_wready WREADY

in

m_axi_bresp BRESP

in [1:0]

m_axi_bvalid BVALID

in

m_axi_bready BREADY

out

m_axi_araddr ARADDR

out [31:0]

m_axi_arprot ARPROT

out [2:0]

m_axi_arvalid ARVALID

out

m_axi_arready ARREADY

in

m_axi_rdata RDATA

in [31:0]

m_axi_rresp RRESP

in [1:0]

m_axi_rvalid RVALID

in

m_axi_rready RREADY

out

Physical Port

Logical Port

Direction

Dependency
up_pll_rst RST

out

Physical Port

Logical Port

Direction

Dependency
* ready

in

Physical Port

Logical Port

Direction

Dependency
* ready

in

Physical Port

Logical Port

Direction

Dependency
* ready

in

Physical Port

Direction

Dependency

Description
up_status

out

Register Map

DWORD

BYTE

Reg Name

Description

BITS

Field Name

Type

Default Value

Description
0x0 0x0 VERSION

Version Register

[31:0] VERSION RO

Version number.
0x1 0x4 ID

Instance Identification Register

[31:0] ID RO

Instance identifier number.
0x2 0x8 SCRATCH

Scratch (GP R/W) Register

[31:0] SCRATCH RW

Scratch register.
0x4 0x10 RESETN

Reset Control Register

[1] BUFSTATUS_RST RW

Initially this flag is held in reset with value 0x1, in order for a user to see the RX BUFSTATUS, this flag needs to be set to 0x0.

[0] RESETN RW

If clear, link is held in reset, set this bit to 0x1 to activate link. Note that the reference clock and DRP clock must be active before setting this bit.
0x5 0x14 STATUS

Status Reporting Register

[6:5] BUFSTATUS RO

BUFSTATUS provides status for either the RX buffer or the TX buffer. If BUFSTATUS is referring to the TX buffer, once BUFSTATUS is set High it remains High until RESETN is activated. Else if BUFSTATUS is referring to the RX buffer, once BUFSTSTATUS is High it can be cleared using BUFSTATUS_RST. If BUFTATUS[6] is 0x1 the internal FIFO overflows and when the BUFSTATUS[5] is 0x1 the internal FIFO underflows. Available from version 17.5.a. For more information consult the transceiver user guide(search for RXBUFSTATUS/TXBUFSTATUS).

[4] PLL_LOCK_N RO

After setting the RESETN bit above, this bit must clear. If does not clears, indicates the CPLL/QPLL did not locked. Available from version 17.4.a

[0] STATUS RO

After setting the RESETN bit above, wait for this bit to set. If set, indicates successful link activation.
0x7 0x1c FPGA_INFO

FPGA device information Xilinx encoded values

[31:24] FPGA_TECHNOLOGY RO

Encoded value describing the technology/generation of the FPGA device (e.g, 7series, ultrascale)

[23:16] FPGA_FAMILY RO

Encoded value describing the family variant of the FPGA device(e.g., zynq, kintex, virtex)

[15:8] SPEED_GRADE RO

Encoded value describing the FPGA’s speed-grade

[7:0] DEV_PACKAGE RO

Encoded value describing the device package. The package might affect high-speed interfaces
0x8 0x20 CONTROL

Transceiver Control Register

[12] LPM_DFE_N RW

Transceiver primitive control, refer Xilinx documentation.

[10:8] RATE RW

Transceiver primitive control, refer Xilinx documentation.

[5:4] SYSCLK_SEL RW

For GTX drives directly the (RX/TX)SYSCLKSEL pin of the transceiver refer to Xilinx documentation. For GTH/GTY drives directly the (RX/TX)PLLCLKSEL pin of the transceiver and indirectly the (RX/TX)SYSCLKSEL pin of the transceiver see Table 1.

[2:0] OUTCLK_SEL RW

Transceiver primitive control Table 2, refer Xilinx documentation.
0x9 0x24 GENERIC_INFO

Physical layer info

[20] QPLL_ENABLE RO

Using QPLL.

[19:16] XCVR_TYPE RO

Xilinx encoded values.

[13:12] LINK_MODE RO

Link layer mode : 01 - 8B10B decoder (aka 204B) 10 - 64B66B decoder (aka 204C); Available from version 17.3.a

[8] TX_OR_RX_N RO

Transceiver type (transmit or receive)

[7:0] NUM_OF_LANES RO

Physical layer number of lanes.
0x10 0x40 CM_SEL

Transceiver Access Register

[7:0] CM_SEL RW

Transceiver common-DRP sel, set to 0xff for broadcast.
0x11 0x44 CM_CONTROL

Transceiver Access Register

[28] CM_WR RW

Transceiver common-DRP sel, set to 0x1 for write, 0x0 for read.

[27:16] CM_ADDR RW

Transceiver common-DRP read/write address.

[15:0] CM_WDATA RW

Transceiver common-DRP write data.
0x12 0x48 CM_STATUS

Transceiver Access Register

[16] CM_BUSY RO

Transceiver common-DRP access busy (0x1) or idle (0x0).

[15:0] CM_RDATA RW

Transceiver common-DRP read data.
0x18 0x60 CH_SEL

Transceiver Access Register

[7:0] CH_SEL RW

Transceiver channel-DRP sel, set to 0xff for broadcast.
0x19 0x64 CH_CONTROL

Transceiver Access Register

[28] CH_WR RW

Transceiver channel-DRP sel, set to 0x1 for write, 0x0 for read.

[27:16] CH_ADDR RW

Transceiver channel-DRP read/write address.

[15:0] CH_WDATA RW

Transceiver channel-DRP write data.
0x1a 0x68 CH_STATUS

Transceiver Access Register

[16] CH_BUSY RO

Transceiver channel-DRP access busy (0x1) or idle (0x0).

[15:0] CH_RDATA RW

Transceiver channel-DRP read data.
0x20 0x80 ES_SEL

Transceiver Access Register

[7:0] ES_SEL RW

Transceiver eye-scan-DRP sel, set to 0xff for broadcast.
0x28 0xa0 ES_REQ

Transceiver eye-scan Request Register

[0] ES_REQ RW

Transceiver eye-scan request, set this bit to initiate an eye-scan, this bit auto-clears when scan is complete.
0x29 0xa4 ES_CONTROL_1

Transceiver eye-scan Control Register

[4:0] ES_PRESCALE RW

Transceiver eye-scan control, refer Xilinx documentation.
0x2a 0xa8 ES_CONTROL_2

Transceiver eye-scan Control Register

[25:24] ES_VOFFSET_RANGE RW

Transceiver eye-scan control, refer Xilinx documentation.

[23:16] ES_VOFFSET_STEP RW

Transceiver eye-scan control, refer Xilinx documentation.

[15:8] ES_VOFFSET_MAX RW

Transceiver eye-scan control, refer Xilinx documentation.

[7:0] ES_VOFFSET_MIN RW

Transceiver eye-scan control, refer Xilinx documentation.
0x2b 0xac ES_CONTROL_3

Transceiver eye-scan Control Register

[27:16] ES_HOFFSET_MAX RW

Transceiver eye-scan control, refer Xilinx documentation.

[11:0] ES_HOFFSET_MIN RW

Transceiver eye-scan control, refer Xilinx documentation.
0x2c 0xb0 ES_CONTROL_4

Transceiver eye-scan Control Register

[11:0] ES_HOFFSET_STEP RW

Transceiver eye-scan control, refer Xilinx documentation.
0x2d 0xb4 ES_CONTROL_5

Transceiver eye-scan Control Register

[31:0] ES_STARTADDR RW

Transceiver eye-scan control, DMA start address (ES data is written to this memory address).
0x2e 0xb8 ES_STATUS

Transceiver eye-scan Status Register

[0] ES_STATUS RO

If set, indicates an error in ES DMA.
0x2f 0xbc ES_RESET

Transceiver eye-scan reset control register

[n] ES_RESETn RW

Controls the EYESCANRESET pin of the GTH/GTY transceivers for lane n. Where n is from 0 to 31.
0x30 0xc0 TX_DIFFCTRL

Transceiver primitive control, refer Xilinx documentation.

[31:0] TX_DIFFCTRL RW

TX driver swing control.
0x31 0xc4 TX_POSTCURSOR

Transceiver primitive control, refer Xilinx documentation.

[31:0] TX_POSTCURSOR RW

Transmiter post-cursor TX pre-emphasis control.
0x32 0xc8 TX_PRECURSOR

Transceiver primitive control, refer Xilinx documentation.

[31:0] TX_PRECURSOR RW

Transmiter pre-cursor TX pre-emphasis control.
0x50 0x140 FPGA_VOLTAGE

FPGA device voltage information

[15:0] FPGA_VOLTAGE RO

The voltage of the FPGA device in mv
0x60 0x180 PRBS_CNTRL

Transceiver PRBS control

[16] PRBSFORCEERR RW

Valid for TX. If set, a single error is forced in the PRBS transmitter for every clock cycle. Can be used to test the PRBS checkers on the other side of the link.

[8] PRBSCNTRESET RW

Valid for RX. Resets the PRBS error counter from the transceiver. Does not self clears. Value of error counter must be accessed via DRP.

[3:0] PRBSSEL RW

PRBS checker or generator test pattern control. All zeros will put the PRBS in bypass mode. For TX non-zero values will stop the normal dataflow from link layer and will inject a pattern instead. See transceiver guide for specific values.
0x61 0x184 PRBS_STATUS

RX Transceiver PRBS status

[8] PRBSERR RO

This sticky status output indicates that PRBS errors have occurred. Value of error counter must be accessed via DRP.

[0] PRBSLOCKED RO

Ignore this bit for GTX transceivers. For others: Indicates that the RX PRBS checker has been error free for 15 XCLK cycles after reset. Once asserted High, it does not deassert until reset of the RX pattern checker via PRBSCNTRESET

Software Guidelines

The system must have active DRP and reference clocks before any software access. The software is expected to write necessary control parameters to LPM_DFE_N, RATE, SYSCLK_SEL, OUTCLK_SEL register bits and then set RESETN bit to 0x1. After that, monitor the STATUS bit to be set. There are no other requirements for initialization.

The DRP access is identical for common and channel interfaces. The SEL bits may be set to a specific transceiver lane or 0xff to broadcast. A write to the CONTROL register (bits WR, ADDR, WDATA) initiates DRP access in hardware. A read to this register has no effect. In order to write to the transceiver, set WR to 0x1 with the address. In order to read from the transceiver, set WR to 0x0 with the address. As soon as this register is written, the BUSY signal is set and is cleared only after the access is complete. The broadcast read is a logical OR of all the channels. After an access is started, do NOT interrupt the core for any reason (including setting RESETN to 0x0), allow the access to finish itself. Though the core itself is immune to a software abort, the transceiver may fail on further accesses and may require a system-wide reset.

The eye-scan feature also allows a SEL option and a broadcast has the effect of a combined mask. That is, the error counter will be zero ONLY if all the transceiver error counters are zero. To start eye-scan, set ES_REQ to 0x1 and wait for the same bit to self-clear. If eye-scan needs to be stopped, set the ES_REQ bit to 0x0.

Table 1

SYSCLK_SEL

00

01

10

11

GTXE2

CPLL

RESERVED

RESERVED

QPLL

GTHE3

CPLL

RESERVED

QPLL1

QPLL0

GTHE4

CPLL

RESERVED

QPLL1

QPLL0

GTYE4

CPLL

RESERVED

QPLL1

QPLL0

Table 2

OUTCLK_SEL

001

010

011

100

101

All other combinations

GTXE2

OUTCLKPCS

OUTCLKPMA

REFCLK

REFCLK/2

RESERVED

RESERVED

GTHE3

OUTCLKPCS

OUTCLKPMA

REFCLK

REFCLK/2

PROGDIVCLK

RESERVED

GTHE4

OUTCLKPCS

OUTCLKPMA

REFCLK

REFCLK/2

PROGDIVCLK

RESERVED

GTYE4

OUTCLKPCS

OUTCLKPMA

REFCLK

REFCLK/2

PROGDIVCLK

RESERVED

The REFCLK selected by OUTCLK_SEL depends on the SYSCLK_SEL, it may be CPLL, QPLL0 or QPLL1 refclk.

Physical layer PRBS testing

The PRBS_CNTRL and PRBS_STATUS registers expose controls of internal PRBS generators and checkers allowing the testing the multi-gigabit serial link at the physical layer without the need of the link layer bringup.

Software Support

References